MD5811-D256-V3Q18-P SanDisk, MD5811-D256-V3Q18-P Datasheet - Page 55

• Manufacturer Part Number: MD5811-D256-V3Q18-P
• Description: IC MDOC P3 256MB 48-TSOP
• Manufacturer: SanDisk

Specifications of MD5811-D256-V3Q18-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 256M (32M x 8)
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.15 DMA Control Register [1:0]
Description:
Address (hex): 1078/107A
52
Read/Write
Description
Reset Value
Read/Write
Description
Reset Value
Bit No.
11-7
6-0
12
13
14
15
SECTOR_COUNT. Specifies the number of 512-byte sectors to be transferred plus one.
Writing a v (a value of 0) indicates a transfer of one sector. Reading a value of 0 indicates
that there is still one sector to be transferred). This field is decremented by Mobile
DiskOnChip P3 after reading the ECC checksum from each sector. In the event of an ECC
error, this field indicates the number of sectors remaining to be transferred.
Reserved for future use.
POLRTY (Polarity). Specifies the polarity of the DMARQ# output:
0: DMARQ# is normally logic -1 and falls to initiate DMA
1: DMARQ# is normally logic -0 and rises to initiate DMA
EDGE. Controls the behavior of the DMARQ# output:
1: DMARQ# pulses to the asserted state for 250 nS (typical) to initiate the block transfer.
0: DMARQ# switches to the active state to initiate the block transfer and returns to the
PAUSE. This bit is set in the event of an ECC error during a DMA operation. After reading
the ECC parity registers and correcting the errors, the software must clear this bit to resume
the DMA operation.
DMA_EN (DMA Enable). Setting this bit enables DMA operation.
DMA_EN
These two 16-bit registers specify the behavior of the DMA operation.
negated state at the beginning of the cycle in which the DCNT field of the ECC Control
register[0] reaches the value specified by the NEGATE_COUNT field of the DMA Control
register[1].
RFU_0
Bit 15
Bit 7
R
0
R
0
PAUSE
Bit 14
Bit 6
0
0
EDGE
Bit 13
Bit 5
R/W
Data Sheet, Rev. 0.3
0
0
POLRTY
Bit 12
Bit 4
Description
0
0
SECTOR_COUNT
Bit 11
Bit 3
R/W
0
0
Bit 10
Bit 2
0
0
RFU_0
R
Bit 1
Bit 9
0
0
Mobile DiskOnChip P3
93-SR-009-8L
Bit 0
Bit 8
0
0