MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet

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MD8331-D2G-V3-X-P

Manufacturer Part Number
MD8331-D2G-V3-X-P
Description
IC MDOC G4 2GB 69-FBGA
Manufacturer
SanDisk
Datasheet

Specifications of MD8331-D2G-V3-X-P

Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
2G (256M x 8)
Speed
33ns
Interface
Parallel
Voltage - Supply
2.5 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
69-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
585-1149-2
MD8831-D2G-V3-X-P
MD8832-D2G-V3-X-P

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Highlights
DiskOnChip G4 is M-Systems' 4
the DiskOnChip family of products. Based on
Multi-Level Cell (MLC) NAND, utilizing
Toshiba’s 90nm MLC NAND Large Block
flash technology and x2 technology from M-
Systems, it is one of the industry’s most
efficient storage solutions. MLC NAND flash
technology provides the smallest die size by
storing 2 bits of information in a single memory
cell. x2 technology enables MLC NAND to
achieve highly reliable, high-performance data
and code storage with a specially designed error
detection and correction mechanism, optimized
file management, and proprietary algorithms for
enhanced performance.
Further cost benefits derive from the
cost-effective architecture of DiskOnChip G4,
which includes a boot block that can replace
expensive NOR flash, and incorporates both the
flash array and an embedded thin controller in a
single die.
DiskOnChip G4 provides:
1
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
Flash disk for both code and data storage
Low voltage: 1.8V core and I/O
Hardware protection and security-enabling
features
High capacity: single die - 1Gb (128MB),
dual die - 2Gb (256MB)
Device cascade capacity: up to 4Gb
(512MB)
Enhanced Programmable Boot Block
enabling eXecute In Place (XIP)
functionality using 16-bit interface
Flash Disk with MLC NAND and M-Systems’ x2 Technology
th
generation of
Data Sheet (Preliminary) Rev. 0.3
Small form factors:
69-ball FBGA 9x12 mm package
Enhanced performance by implementation
of:
Unrivaled data integrity with a robust Error
Detection Code/Error Correction Code
(EDC/ECC) tailored for MLC NAND flash
technology
Maximized flash endurance with TrueFFS
6.3.2 (and higher)
Support for major operating systems (OSs),
including Symbian OS, Microsoft Windows
Mobile, Palm OS, Nucleus, Linux, OSE,
Windows CE, and more.
Compatible with major CPUs, including
TI OMAP, TI DBB, Intel XScale, Infinion,
EGold and SGold, ADI 652x, Freescale
MX, and Qualcomm MSMxxxx.
DMA support
MultiBurst operation
Data Sheet, November 2005
92-DS-1105-00
®

Related parts for MD8331-D2G-V3-X-P

MD8331-D2G-V3-X-P Summary of contents

Page 1

... Systems one of the industry’s most efficient storage solutions. MLC NAND flash technology provides the smallest die size by storing 2 bits of information in a single memory cell. x2 technology enables MLC NAND to achieve highly reliable, high-performance data and code storage with a specially designed error ...

Page 2

Performance MultiBurst read: 15 MB/sec Sustained read: 9 MB/sec Sustained write: 2.4 MB/sec Access time: Normal: 33 nsec Protection & Security-Enabling Features 16-byte Unique Identification (UID) number 16KByte user-controlled One Time Programmable (OTP) area Two configurable hardware-protected partitions for data ...

Page 3

TrueFFS Software Full hard-disk read/write emulation for transparent file system management Patented TrueFFS Flash file system management Automatic block management Data management to maximize the limit of typical flash life expectancy Dynamic virtual mapping Dynamic and static wear-leveling Programming, ...

Page 4

R H EVISION ISTORY Doc. No Revision 92-DT-0305-00 0.1 0.2 92-DS-1105-00 0.3 4 Date Description March 2005 Preliminary version October 2005 Device ball number was reduced from 115 to 69 balls (only not connected balls were reduced). Updated mechanical dimensions. ...

Page 5

T C ABLE OF ONTENTS 1. Introduction ............................................................................................................................... 9 2. Product Overview .................................................................................................................... 10 2.1 Product Description .......................................................................................................... 10 2.2 Standard Interface ............................................................................................................ 11 2.2.1 Ball Diagrams ..................................................................................................................... 11 2.2.2 System Interface ................................................................................................................ 12 2.2.3 Signal Description .............................................................................................................. 13 2.3 ...

Page 6

... Wear-Leveling .................................................................................................................... 34 6.4.7 Power Failure Management ............................................................................................... 35 6.4.8 Error Detection/Correction.................................................................................................. 36 6.4.9 Special Features Through I/O Control (IOCTL) Mechanism.............................................. 36 6.4.10 Compatibility ....................................................................................................................... 36 6.5 8KB Memory Window ....................................................................................................... 36 7. Register Descriptions ............................................................................................................. 38 7.1 Definition of Terms ........................................................................................................... 38 7.2 Reset Values .................................................................................................................... 39 7.3 RAM Page Command Register ........................................................................................ 39 7.4 RAM Page Select Register............................................................................................... 39 7 ...

Page 7

DPD Control Register ....................................................................................................... 46 7.19 DMA Control Register [1:0]............................................................................................... 47 7.20 MultiBurst Mode Control Register..................................................................................... 48 7.21 Virtual/Paged RAM Status Register ................................................................................. 49 8. Booting from DiskOnChip G4................................................................................................. 51 8.1 Introduction....................................................................................................................... 51 8.2 Boot Replacement ............................................................................................................ 51 8.2.1 ...

Page 8

Capacitance........................................................................................................................ 64 10.2.3 DC Electrical Characteristics over Operating Range ......................................................... 65 10.2.4 AC Operating Conditions.................................................................................................... 67 10.3 Timing Specifications........................................................................................................ 68 10.3.1 Read Cycle Timing Standard Interface .............................................................................. 68 10.3.2 Write Cycle Timing Standard Interface .............................................................................. 71 10.3.3 Read Cycle ...

Page 9

... Major features and benefits of x2 technology Section 4: Detailed description of hardware protection and security-enabling features Section 5: Detailed description of modes of operation and TrueFFS technology, including Section 6: power failure management and 8KByte memory window DiskOnChip G4 register descriptions Section 7: Overview of how to boot from DiskOnChip G4 Section 8: Hardware and software design considerations ...

Page 10

... DiskOnChip G4 has a 2KB Programmable Boot Block. This block provides eXecute In Place (XIP) functionality, enabling DiskOnChip G4 to replace the boot device and function as the only non-volatile memory device on-board. Eliminating the need for an additional boot device reduces hardware expenditures, board real estate, programming time, and logistics. ...

Page 11

Standard Interface 2.2.1 Ball Diagrams See Figure 1 for the DiskOnChip G4 128MB (1Gb)/256MB (2Gb) ballout for the standard interface. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should not be connected. Note: ...

Page 12

System Interface See Figure 2 for a simplified I/O diagram for a standard interface of DiskOnChip G4 128MB (1Gb) and 256MB (2Gb). CE#. OE 15:0 System Interface Figure 2: Standard Interface Simplified I/O ...

Page 13

... Chip 3 = ID1, ID0 = VCCQ, VSS (1,0) Chip 4 = ID1, ID0 = VCCQ, VCCQ (1,1) DiskOnChip G4 256MB(2Gb) supports up to two chips cascaded in the same memory window: Chip 1 = ID1, ID0 = VSS, VSS (0,0); must be used for single chip configuration Chip 2 = ID1, ID0 = VCCQ, VCCQ (1,1) ST Lock, active low ...

Page 14

Signal Ball No. BUSY# E5 RSTIN# D5 CLK K6 DMARQ# G8 IRQ# F9 DPD G2 VCC J5 VCCQ J6 VSS G3, J9 RSRVD See Figure The following abbreviations are used Standard (non-Schmidt) input ...

Page 15

Multiplexed Interface 2.3.1 Ball Diagram See Figure 3 for the DiskOnChip G4 ballout for the multiplexed interface. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should not be connected. Note: Forth-generation DiskOnChip G4 ...

Page 16

System Interface See Figure 4 for a simplified I/O diagram of DiskOnChip G4 WE 15:0 System Interface Figure 4: Multiplexed Interface Simplified I/O Diagram 16 DiskOnChip ID0 AVD# ...

Page 17

... Output Enable, active low Configuration Address Valid. Set multiplexed interface Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1 = ID0 = VSS; must be used for single-chip configuration Chip 2 = ID0 = VCC Lock, active low. When active, provides full hardware data protection of selected partitions ...

Page 18

Input Signal Pin No. Type DPD G2 ST VCC J5 - VCCQ J6 VSS G3, J9, D8, - C8, F7, E7, C7, C3, D3, E3, F3, D2, E2, F2 RSRVD See Figure The following ...

Page 19

T O HEORY OF PERATION 3.1 Overview DiskOnChip G4 consists of the following major functional blocks, as shown in Figure 5. *ADDR[0] and DPD are multiplexed on the same ball/pin. Figure 5: Simplified Block Diagram, Standard Interface These components ...

Page 20

... In addition, the EEPROM-like interface enables direct access to the Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system initialization. A 13-bit wide address bus enables access to the DiskOnChip G4 8KB memory window (as shown in Section 6.5). The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and write cycles ...

Page 21

... Read/Write Protection Data and code protection is implemented through a Protection State Machine (PSM). The user can configure one or two independently programmable areas of the flash memory as read protected, write protected, or read/write protected. A protected partition may be protected by either/both of these hardware mechanisms: • 64-bit protection key • ...

Page 22

One-Time Write (ROM-Like) Partition A partition in the DiskOnChip G4 can be set as One-Time Write. After it is locked, this partition becomes read only, just like a ROM device. Its capacity is defined during the media-formatting stage. 3.4.5 ...

Page 23

During the download process, DiskOnChip G4 asserts the BUSY# signal to indicate to the system that it is not yet ready to be accessed. Once BUSY# is negated, the system can access DiskOnChip G4. A failsafe mechanism prevents improper initialization ...

Page 24

DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V Figure 6: Page Structure Bytes Figure 7: Block Structure Data Sheet (Preliminary) Rev. 0.3 Page 0 Page 1 256 KB Page 126 Page 127 92-DS-1105-00 ...

Page 25

T X ECHNOLOGY DiskOnChip G4 enhances performance using various proprietary techniques: • MultiBurst operation to read large chunks of data, providing a MultiBurst read speed MB/sec. • DMA operation to release the CPU for ...

Page 26

MultiBurst operation is controlled by 5 bits in the MultiBurst Mode Control register: BURST_EN, CLK_INV, LATENCY, HOLD and LENGTH. For full details on this register, please refer to Section 7. MultiBurst mode read cycles are supported via the CLK input, ...

Page 27

FIFO mode: Enables FIFO in the data path. The FIFO outputs data on each cycle of the CLK input, while the FIFO is filled with Flash data on every other cycle. o 16-bit hosts: Burst length is limited to ...

Page 28

DMA Operation DiskOnChip G4 provides a DMARQ# output that enables up to 256KB to be read from the flash by the host DMA controller. During DMA operation, the DMARQ# output is used to notify the host DMA controller that ...

Page 29

Combined MultiBurst Mode and DMA Operation When using MultiBurst mode and DMA operation together, and an interrupt is generated (IRQ# signal asserted), the Download Status register cannot be polled will not comply with the MultiBurst mode timing ...

Page 30

H P ARDWARE ROTECTION 5.1 Method of Operation DiskOnChip G4 enables the user to define two partitions that are protected (in hardware) against any combination of read or write operations. The two protected areas can be configured as read ...

Page 31

M O ODES OF PERATION DiskOnChip G4 operates in one of three basic modes: • Normal mode • Reset mode • Deep Power-Down mode The current mode of the chip can always be determined by reading the DiskOnChip Control ...

Page 32

... Normal Mode This is the mode in which standard operations involving the flash memory are performed. Normal mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control Confirmation register. A write cycle occurs when both the CE# and WE# inputs are asserted. ...

Page 33

... TrueFFS Technology 6.4.1 General Description M-Systems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk, making it completely transparent to the OS. In addition, since it operates under the OS file system layer (see Figure 10 completely transparent to the application ...

Page 34

... Wear-Leveling Flash memory can be erased a limited number of times. This number is called the erase cycle limit , or write endurance limit , and is defined by the flash array vendor. The erase cycle limit applies to each individual erase block in the flash device. ...

Page 35

... If wear-leveling were only applied on newly written pages, static areas would never be cycled. This limited application of wear-leveling would lower life expectancy significantly in cases where flash memory contains large static areas. To overcome this problem, TrueFFS forces data transfer in static areas as well as in dynamic areas, thereby applying wear-leveling to the entire media ...

Page 36

... The 2KB Programmable Boot Block is in section 0 and section 3, to support systems that search for a checksum at the boot stage both from the top and bottom of memory. The addresses described here are relative to the absolute starting address of the 8KB memory window. ...

Page 37

... Programmable Programmable Boot Block Boot Block Section 0 800H Flash area 00H Section 1 (+ aliases) 00H Section 2 Registers Programmable Programmable Boot Block Boot Block Section 3 Figure 11: DiskOnChip G4 Memory Map Data Sheet (Preliminary) Rev. 0.3 DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V window Control 92-DS-1105-00 ...

Page 38

R D EGISTER ESCRIPTIONS This section describes various DiskOnChip G4 registers and their functions, as listed in Table 3. Most DiskOnChip G4 registers are 8-bit, unless otherwise denoted as 16-bit. Address (Hex) 0030 0070 0080 100A 100C 100E 101C ...

Page 39

Reset Values All registers return 00H while in Reset mode. The Reset value written in the register description is the register value after exiting Reset mode and entering Normal mode. Some register contents are undefined at that time (N/A). ...

Page 40

Paged RAM Unique ID Download Register Description: Writing to this 8 bit register initiates a download of the 16-byte Unique Identification (UID) number to offset 0 of the downloadable section of the IPL RAM .After polling for ready status, ...

Page 41

... Test Register Description: This register enables software to identify multiple DiskOnChip G4 devices or multiple aliases in the CPUs memory space. Data written is stored but does not affect the behavior of DiskOnChip G4. Address (hex): 1004 Type: Read/Write Reset Value: 0 Bit No. 7-0 D[7:0]: Data bits 7.9 Endian Control Register ...

Page 42

... G4 operational mode. After writing the required value to the DiskOnChip Control register, the complement of that data byte must also be written to the Control Confirmation register. The two writes cycles must not be separated by any other read or write cycles to the DiskOnChip G4 memory space, except for reads from the Programmable Boot Block space. Address ...

Page 43

Device ID Select Register Description cascaded configuration, this register controls which device provides the register space. The value of bits ID[0:1] is compared to the value of the ID configuration input pins/balls. The device whose ID input ...

Page 44

Interrupt Control Register Description: This 16-bit register controls how interrupts are generated by DiskOnChip G4, and indicates which of the following five sources has asserted an interrupt: 0: Flash array is ready 1: Data protection violation 2: Reading or ...

Page 45

Bit No. 15 GMASK (Global Mask). 1: Enables the IRQ# output to be asserted. Setting this bit while one or more interrupts are pending will generate an interrupt. 0: Forces the IRQ# output to the negated state. 7.14 Interrupt Status ...

Page 46

PU_DIS (Pull-Up Disable). Controls the pull-up resistors D[15:8] as follows: 1: Always disable the pull-ups 0: Enable the pull-ups when IF_CFG = 0 2 TURBO. Activates turbo ...

Page 47

DMA Control Register [1:0] Description: These two 16-bit registers specify the behavior of the DMA operation. Address (hex): 1078/107A Bit 7 Bit 6 Read/Write R Description RFU_0 0 Reset Value Bit 15 Bit 14 Read/Write R Description DMA_EN PAUSE ...

Page 48

Read/Write Description Reset Value 0 Bit No. 9-0 NEGATE_COUNT. When the EDGE bit of the DMA Control register[ this field must be programmed to specify the bus cycle in which DMARQ# will be negated, as follows: NEGATE_COUNT = ...

Page 49

... RAM downloads to permit polling for ready status after a software reset. Address (hex): 1024 Bit 7 Bit 6 Read/Write R Description VRS Reset Value 1 Bit No. 0 VR_EN [Virtual RAM Enable] Indicates that Virtual RAM is enabled. 1 ALT_MAP [Alternate Memory Map] VR_EN = 1: Controls initial data in RAM after a hardware or software reset as follows: 49 Bit 5 Bit 4 Bit RFU_0 VR_DIS Description Data Sheet (Preliminary) Rev ...

Page 50

... Paged RAM command sequence. After the initial download, the data in the upper and lower 1KB pages is swapped compared to the case of Alternate Memory Map = 0. 3 VR_DIS [Virtual RAM Disable] Setting this bit prevents Virtual RAM downloads from occurring ...

Page 51

... When DiskOnChip G4 is configured with the Virtual RAM Boot feature active, DiskOnChip remains in virtual RAM whenever Reset mode. While in this mode, read cycles from the entire DiskOnChip 8KB memory window return virtual RAM data. Access to an address that is not the physical 2KB SRAM initiates a download operation in which the required data is copied from the NAND flash to the physical SRAM ...

Page 52

... Normally, the data in the first 1KB of RAM is fixed, while the second downloaded upon command. To support platforms that boot from the top rather than the bottom of memory, DiskOnChip G4 can be configured with an alternate memory map where the top 1KB of the DiskOnChip G4 address space returns fixed RAM data, while the 1KB below that is downloadable. ...

Page 53

... ONSIDERATIONS 9.1 General Guidelines A typical RISC processor memory architecture is shown in Figure 12. It may include the following devices: • DiskOnChip G4 : Contains the OS image, applications, registry entries, back-up data, user files and data, etc. It can also be used to perform boot operation, thereby replacing the need for a separate boot device ...

Page 54

... Standard NOR-Like Interface DiskOnChip G4 uses a NOR-like interface that can easily be connected to any microprocessor bus. With a standard interface, it requires 13 address lines, 8 data lines and basic memory control signals (CE#, OE#, WE#), as shown in Figure 13 below. Typically, DiskOnChip G4 can be mapped to any free 8KB memory space. ...

Page 55

Notes: 1. The 0.1 µF and the 10 nF low-inductance, high-frequency capacitors must be attached to each of the device’s VCC and VSS balls. These capacitors must be placed as close as possible to the package leads. 2. DiskOnChip G4 ...

Page 56

... Output Enable (OE#) and Write Enable (WE#) – Connect these signals to the host RD# and WR# signals, respectively. • Chip Enable (CE#) – Connect this signal to the memory address decoder. Most RISC processors include a programmable decoder to generate various Chip Select (CS) outputs for 56 1.8V 0 ...

Page 57

... These CS signals can be programmed to support different wait states to accommodate DiskOnChip G4 timing specifications. • Power-On Reset In (RSTIN#) – Connect this signal to the host active-low Power-On Reset signal. • Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 13. Both signals must be connected to VSS if the host uses only one DiskOnChip ...

Page 58

Implementing the Interrupt Mechanism 9.5.1 Hardware Configuration To configure the hardware for working with the interrupt mechanism, connect the IRQ# pin/ball to the host interrupt input. Note: A nominal 10 KΩ pull-up resistor must be connected to this pin/ball. ...

Page 59

Device Cascading When connecting DiskOnChip G4 128MB (1Gb) using a standard interface four devices can be cascaded with no external decoding circuitry. Figure 15 illustrates the configuration required to cascade four devices on the host bus (only ...

Page 60

Boot Replacement A typical RISC architecture uses a boot ROM for system initialization. The boot ROM is also required to access DiskOnChip G4 during the boot sequence in order to load OS images and the device drivers. M-Systems’ Boot ...

Page 61

Platform-Specific Issues This section discusses hardware design issues for major embedded RISC processor families. 9.8.1 Wait State Wait states can be implemented only when DiskOnChip G4 is designed in a bus that supports a Wait state insertion, and supplies ...

Page 62

Data Access Mode When configured for 8-bit operation, pin/ball IF_CFG should be connected to VSS, and data lines D[15:8] are internally pulled up and may be left unconnected. The controller routes odd and even address accesses to the ...

Page 63

Design Environment DiskOnChip G4 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and development with DiskOnChip G4, even before the target platform is available. • Programming solutions: Programmer Programming house On-board programming ...

Page 64

P S RODUCT PECIFICATIONS 10.1 Environmental Specifications 10.1.1 Operating Temperature Commercial temperature range: Extended temperature range: -40°C to +85°C 10.1.2 Thermal Characteristics Junction to Case (θ 10.1.3 Humidity 10% to 90% relative, non-condensing 10.2 Electrical Specifications 10.2.1 Absolute Maximum ...

Page 65

Input capacitance (256MB/2Gb device) Output capacitance (128MB/1Gb device) C OUT Output capacitance (256MB/2Gb device) Capacitance is not 100% tested. 10.2.3 DC Electrical Characteristics over Operating Range See Table 8 for DC characteristics for VCCQ ranges 1.65-1.95V Table 8: DC Characteristics, ...

Page 66

Symbol Parameter Standby supply current I CCqs VCCQ 1. VCCQ VCC= = 1.8V, Outputs open 2. The CE# input includes a pull-up resistor which sources 0.3~3 Vin=0V 3. Deep Power-Down mode is achieved by asserting RSTIN# (when in ...

Page 67

AC Operating Conditions Timing specifications are based on the conditions defined below. Ambient temperature (TA) Core supply voltage (VCC) Input pulse levels Input rise and fall times Input timing levels Output timing levels Output Load, D[15:0] Output Load, IRQ#, ...

Page 68

Timing Specifications 10.3.1 Read Cycle Timing Standard Interface t (A) SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 18: Standard Interface, Read Cycle Timing t (A) SU A[12:0] CE# t (CE1) HO OE# WE# D[15:0] Figure 19: ...

Page 69

Table 10: Standard Interface Read Cycle Timing Parameters Symbol Tsu(A) Address to OE# Tsu(A-OE1) Address to OE# Tw(OE0) OE# low pulse width Tho(A) OE# Tsu(CE0) CE# Tho(CE0) OE# Tho(CE1) OE# or WE# CE# Tsu(CE1) time Trec(OE) OE# negated to start ...

Page 70

Tacc + tho(A1-D). 9. Tcyc(A1) is effectively limited by Tacc(A1). 10. trec(A1) is measured from the last A[1] transition which clocks data out to the assertion of (CE# and OE#) or (CE# and WE#) ...

Page 71

Write Cycle Timing Standard Interface t SU A[12:0] t (CE1) HO CE# OE# WE# D[15:0] Figure 21: Standard Interface Write Cycle Timing Table 11: Standard Interface Write Cycle Parameters Symbol T (A) Address to WE# SU Tho(A) WE# Tw(WE) ...

Page 72

Read Cycle Timing Multiplexed Interface t W AVD# t (AVD) SU AD[15:0] CE# t (CE1) HO OE# WE# Figure 22: Multiplexed Interface Read Cycle Timing Table 12: Multiplexed Interface Read Cycle Parameters Symbol Tsu(AVD) Address to AVD# Tho(AVD) AVD# ...

Page 73

Start of A[1] single transition T (A1) 1X region before OE# Tacc(A1) Access time from A[1] Tho(A1-D) A[ output hold time Tsu(A1-OE0) A[1] to OE# Tho(OE1-A1) OE# Tho(OE0-A1) OE# Tho(A1-OE1) A[1] to OE# Trec(A1) A[1] to start of ...

Page 74

Write Cycle Timing Multiplexed Interface AVD# t (AVD) SU AD[15:0] t (CE1) HO CE# OE# WE# Figure 23: Multiplexed Interface Write Cycle Timing Table 13: Multiplexed Interface Write Cycle Parameters Symbol Trec(WE-AVD) WE# Tsu(AVD) Address to AVD# Tho(AVD) Address ...

Page 75

CE# may be asserted any time before or after WE# is asserted. If CE# is asserted after WE#, all timing relative to WE# asserted will be referenced instead to the time of CE# asserted. 2. CE# may be negated ...

Page 76

Read Cycle Timing MultiBurst In Figure 24, the MultiBurst Control register values are: LATENCY=0, LENGTH=4, CLK_INV=0. t (CLK1) W CLK t (OE0-CLK0) HO OE# t (OE0-CLK1 (OE0-CLK1) SU WE# t (A) SU A[12:0] D[15:0] (HOLD=0) D[15:0] (HOLD=1) ...

Page 77

Symbol CLK high pulse width CLK low pulse width CLK low pulse width CLK low pulse width T (CLK0) W CLK low pulse width CLK low pulse width CLK low pulse width CLK period CLK period CLK period T(CLK) CLK ...

Page 78

Flash Characteristics Table 15: Flash Program, Erase, and Read Timing Symbol T Page programming time PROG T Block erasing time ERASE Even page reading time T READ Odd page reading time 10.3.7 Power Supply Sequence When operating DiskOnChip G4 ...

Page 79

... Power-Up Timing DiskOnChip G4 is reset by assertion of the RSTIN# input. When this signal is negated, DiskOnChip G4 initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this procedure, DiskOnChip G4 does not respond to read or write accesses. Host systems must therefore observe the requirements described below for first access to DiskOnChip G4 ...

Page 80

VCC & VCCQ within operating specifications VCC RSTIN# BUSY# A[12:0] CE#, OE# (WE (Read cycle) AVD# (Muxed Mode Only) DPD (A[0]) Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width W T ...

Page 81

Applies to multiplexed interface only. 5. Applies to SRAM mode only. 6. DPD transition refers to exiting Deep Power Down mode by toggling DPD (A[0]). 7. 10.3.9 Interrupt Timing IRQ# Symbol Tw(IRQ#) IRQ# asserted pulse width (Edge mode) 10.3.10 ...

Page 82

Tp(OE-DMARQ1) 2,3,7 Tp(OE-DMARQ0) 2,4,6 Tp(CLK0-DMARQ1) 2,4,7 Tp(CLK0-DMARQ0) 2,5,6 Tp(CLK1-DMARQ1) 2,5,7 Tp(CLK1-DMARQ0) 1. Applies to Edge mode only. 2. Applies to Level mode only. 3. Applies to non-burst mode. 4. Applies to normal-burst mode 5. Applies to FIFO-burst and HOLD-burst ...

Page 83

Mechanical Dimensions FBGA 128MB (1Gb) dimensions: 9.0 ±0. 12.0 ±0. 1.1 ±0.1 mm FBGA 256MB (2Gb) dimensions: 9.0 ±0. 12.0 ±0. 1.3 ±0.1 mm Ball pitch: 0.8 mm 9.0 12.0 Figure ...

Page 84

... O I RDERING NFORMATION Refer to Table 19 for combinations currently available and the associated order numbers. Ordering Code MD8832-d1G-V18-X-P MD8331-d2G-V18-X-P MD8832-d00-DAISY-P MD8832-d1Gb-MECH 84 Table 19: Available Combinations Capacity Core Voltage MB Mb [V] 128 1024 BGA 69 (1Gbit) balls 1.8 2048 BGA 69 256 (2Gbit) balls 69-ball FBGA 9x12 00 000 ...

Page 85

ONTACT S USA M-Systems, Inc. 555 North Mathilda Avenue, Suite 220 Sunnyvale, CA 94085 Phone: +1-408-470-4440 Fax: +1-408-470-4470 Japan M-Systems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: ...

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