MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 57

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

9.4.2
DiskOnChip G4 can use a multiplexed interface to connect to the multiplexed bus (asynchronous
read/write protocol). In this configuration, the ID[1] input is driven by the host's AVD# signal, and
the D[15:0] pins/balls, used for both address inputs and data, are connected to the host AD[15:0]
bus. As with a standard interface, only address bits [12:0] are significant.
This mode is automatically entered when a falling edge is detected on ID[1]. This edge must occur
after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read cycle made to
DiskOnChip must observe the multiplexed mode protocol. See Section 10.3 for more information
about the related timing requirements.
Please refer to Section 2.3 for pinout and signal descriptions, and to Section 10.3 for timing
specifications for a multiplexed interface.
57
• Power-On Reset In (RSTIN#) – Connect this signal to the host active-low Power-On Reset
• Chip Identification (ID[1:0]) – Connect these signals as shown in Figure 13. Both signals
• Busy (BUSY#) – This signal indicates when the device is ready for first access after reset. It
• DMARQ# (DMA Request) – Output used to control multi-page DMA operations. Connect
• IRQ# (Interrupt Request) – Connect this signal to the host interrupt.
• Lock (LOCK#) – Connect to a logical 0 to prevent the usage of the protection key to open a
• Deep-Power Down (DPD) – multiplexed with A[0].
• 8/16 Bit Interface Configuration (IF_CFG) – This signal is required for configuring the
• Clock (CLK) – This input is used to support MultiBurst operation when reading flash data.
different memory zones. These CS signals can be programmed to support different wait
states to accommodate DiskOnChip G4 timing specifications.
signal.
must be connected to VSS if the host uses only one DiskOnChip. If more than one device is
being used, refer to Section 9.6 for more information on device cascading.
may be connected to an input port of the host, or alternatively it may be used to hold the host
in a wait-state condition. The later option is required for hosts that boot from DiskOnChip
G4.
this output to the DMA controller of the host platform.
protected partition. Connect to logical 1 in order to enable usage of protection keys.
device for 8- or 16-bit access mode. When negated, the device is configured for 8-bit access
mode. When asserted, 16-bit access mode is operative.
Refer to Section 4.1 for further information on MultiBurst operation.
Multiplexed Interface
Data Sheet (Preliminary) Rev. 0.3
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00