MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 73

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

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CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be
referenced instead to the time of CE# asserted.
CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.
No load (CL = 0 pF).
A[1] may have no more than 1 transition in the region between t1X(A1) and tsu(A), and may have no transitions between tsu(A) and tho(A).
trec(A1) is measured from the last A[1] transition which clocks data out to the assertion of (CE# and OE#) or (CE# and WE#).
Please refer to Figure 20 and disregard parameters tho(A) and tsu(A) which are applicable only to the SRAM interface. For the Muxed
interface, Tsu(AVD), Tho(AVD), Tw(AVD) and Tho(AVD-OE) apply to Paged mode read cycles as shown in Figure 20
Paged Mode is supported only when reading from the Flash Data Register.
Tho(OE1-A1)
Tho(OE0-A1)
Tho(A1-OE1)
Tsu(A1-OE0)
Tho(A1-D)
Tacc(A1)
Tcyc(A1)
Trec(A1)
T
1X
(A1)
Start of A[1] single transition
region before OE#
Access time from A[1]
A[1] to D output hold time
A[1] to OE#
OE#
OE#
A[1] to OE#
A[1] to start of next cycle
Time between A[1] transitions
to A[1] hold time
to A[1] hold time
Data Sheet (Preliminary) Rev. 0.3
setup time
hold time
4
2
2
1
5
1
3
-19
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
30
10
33
61
98
60
-9
56
ns
ns
ns
ns
ns
ns
ns
ns
ns
92-DS-1105-00