MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 32

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

6.1
This is the mode in which standard operations involving the flash memory are performed. Normal
mode is entered when a valid write sequence is sent to the DiskOnChip Control register and Control
Confirmation register. A write cycle occurs when both the CE# and WE# inputs are asserted.
Similarly, a read cycle occurs when both the CE# and OE# inputs are asserted. Because the flash
controller generates its internal clock from these CPU bus signals and some read operations return
volatile data, it is essential that the timing requirements specified in Section 10.3 be met. It is also
essential that read and write cycles not be interrupted by glitches or ringing on the CE#, WE#, and
OE# inputs. All inputs to DiskOnChip G4 are Schmidt Trigger types to improve noise immunity.
6.2
In Reset mode, DiskOnChip G4 ignores all write cycles, except for those to the DiskOnChip
Control register and Control Confirmation register. All register read cycles return a value of 00H.
Before attempting to perform any operation, the device is set to Normal mode by TrueFFS software.
6.3
While in Deep Power-Down mode, DiskOnChip G4’s quiescent power dissipation is reduced by
disabling internal high current consumers (e.g. voltage regulators, input buffers, oscillator etc.). The
following signals are also disabled in this mode:
To enter Deep Power-Down mode, a proper sequence must be written to the DiskOnChip G4
Control registers and the CE# input must be negated. All other inputs should be VSS or VCC.
Asserting the RSTIN# signal and holding it in low state puts the device in Deep Power-Down mode.
When the RSTIN# signal is released, the device is left in Reset mode.
Toggling the DPD signal, as defined by the DPD Control register, puts the device in Power-Down
mode as well.
In Deep Power-Down mode, write cycles have no effect and read cycles return indeterminate data
(DiskOnChip G4 does not drive the data bus). Entering Deep Power-Down mode and then returning
to the previous mode does not affect the value of any register.
To exit Deep Power-Down mode, use one of the following methods:
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• Standard interface : Input buffers A[12:0], WE#, D[15:0] and OE# (when CE# is negated)
• Multiplexed interface : Input buffers AD[15:0], AVD#, WE# and OE# (when CE# is
• Read twelve times from address 1FFFH (Programmable Boot Block). The data returned is
• Perform a single read cycle from the Programmable Boot Block with an extended access
Normal Mode
Reset Mode
Deep Power-Down Mode
negated).
undefined.
time and address hold time as specified in the timing diagrams. The data returned will be
correct. Please note that this option can only be used with a standard interface, not with a
multiplexed interface.
Data Sheet (Preliminary) Rev. 0.3
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
92-DS-1105-00