MD8331-D2G-V3-X-P SanDisk, MD8331-D2G-V3-X-P Datasheet - Page 49

• Manufacturer Part Number: MD8331-D2G-V3-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V3-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 2.5 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1149-2; MD8831-D2G-V3-X-P; MD8832-D2G-V3-X-P

7.19 Virtual/Paged RAM Status Register
Description:
Address (hex): 1024
49
Read/Write
Description
Reset Value
Bit No.
12-15
8-11
6-7
2
3
4
5
0
1
HOLD. Specifies if the data output on D[15:0] during MultiBurst mode read cycles should be
held for an additional clock cycle.
0: Data on the D[15:0] outputs is held for one clock cycle
1: Data on the D[15:0] outputs is held for two clock cycles
FIFO. Enables FIFO mode which supports higher CLK frequencies but imposes limitations
on LENGTH and LATENCY. This bit must not be set if HOLD=1
EBRA (Exit Burst on RAM Access). Enables asynchronous sampling of A[12:11] at the start
of each cycle. If a RAM read access is detected while EBRA is set, then BST_EN will be
negated and the RAM access will be completed asynchronously
LATPI (Latency Plus 1). Externally, setting this bit is equivalent to adding an additional clock
cycle of latency. Internally, however, it eliminates a critical timing path which occurs when
FIFO=1 and EBRA=1.
Reserved for future use.
LATENCY. Controls the number of clock cycles between when DiskOnChip G4 samples
OE# and CE# asserted and the first word of data is available to be latched by the host. This
number of clock cycles is equal to 2 + LATECNCY. If HOLD = 1, then the data is available
to be latched on this clock and on the subsequent clock.
LENGTH. Specifies the number of byte/words (depending on IF_CFG) to be transferred in
each burst cycle:
HOLD=0: Number of bytes/words = 2 ^ LENGTH
HOLD=1: Number of bytes/words = 2 ^ (LENGTH – 1)
Note: The maximum value of LENGTH is 10.
VR_EN [Virtual RAM Enable] Indicates that Virtual RAM is enabled.
ALT_MAP [Alternate Memory Map]
VR_EN = 1: Controls initial data in RAM after a hardware or software reset as follows:
The 3 LSBs of this 8 bit register indicate the value of the Virtual/Paged RAM
status byte. This register also provides a means of temporarily disabling Virtual
RAM downloads to permit polling for ready status after a software reset.
clock delay from CE#/OE# asserted until the first data word may be latched on D[15:0].
Bit 7
VRS
R
1
Bit 6
R
0
Data Sheet (Preliminary) Rev. 0.3
RFU_0
Bit 5
R
0
Bit 4
R
0
Description
VR_DIS
Bit 3
RW
0
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
Bit 2
RFU
R
ALT_MAP
Varies
Bit 1
R
92-DS-1105-00
VR_EN
Bit 0
R