MD2533-D8G-X-P SanDisk, MD2533-D8G-X-P Datasheet
MD2533-D8G-X-P
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MD2533-D8G-X-P Summary of contents
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... hybrid device combining an embedded thin flash controller and standard flash memory. In addition to the high reliability and high system performance offered by the current mDOC family of products, mDOC H3 offers plug-and-play integration, support for multiple NAND technologies and more features such as advanced power management schemes ...
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Embedded TrueFFS enables mDOC H3 to fully emulate a hard disk to the host processor, enabling read/write operations that are identical to a standard, sector-based hard drive. In addition, Embedded TrueFFS employs patented methods, such as virtual mapping, dynamic and ...
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Ball to ball compatible with mDOC G3/G4/H1 product families. Enhanced performance by implementation of: Multi-plane operations DMA support Burst operation Dual Data RAM buffering Read/Write Cache Unrivaled data integrity with a robust 6 bit Error Detection Code/Error Correction Code (EDC/ECC) ...
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Freescale i.MXxx Application processors and i.xx digital Baseband devices Zoran ER4525 Renesas SH mobile EMP platforms Qualcomm MSMxxxx Hitachi SuperH™ SH-x Supports 16 and 32-bit architectures E T FFS S MBEDDED RUE TrueFFS (True Flash File System) is mystems’ acclaimed ...
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R H EVISION ISTORY Doc. No Revision 92-DS-1205-10 0.1 0.2 5 Date Description January 2006 Preliminary version June 2006 RSRVD balls left floating changed from a recommendation to a requirement Standard I/F Ball H9 changed from RSRVD to VSS Ballout ...
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T C ABLE OF ONTENTS 1. Introduction..............................................................................................................................10 2. Product Overview ....................................................................................................................11 2.1 Product Description ..........................................................................................................11 2.2 Standard Interface ............................................................................................................13 2.2.1 9x12/12x18 FBGA Ball Diagrams .......................................................................................13 2.2.2 9x12/12x18 FBGA Signal Description.................................................................................15 2.2.3 System Interface .................................................................................................................18 2.3 Multiplexed Interface.........................................................................................................19 2.3.1 9x12/12x18 FBGA ...
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... Power Failure Management ................................................................................................36 6.3.5 Error Detection/Correction ..................................................................................................36 6.3.6 Special Features through I/O Control (IOCTL) Mechanism................................................36 6.3.7 Compatibility........................................................................................................................36 6.4 128KB Memory Window ...................................................................................................38 6.5 8KB Memory Window .......................................................................................................39 7. mDOC H3 Registers ................................................................................................................40 7.1 Definition of Terms............................................................................................................40 7.2 Reset Values ....................................................................................................................41 7.3 Registers Description........................................................................................................41 7.3.1 Paged RAM Command Register.........................................................................................41 7 ...
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Introduction .......................................................................................................................52 8.1.1 Asynchronous Boot Mode ...................................................................................................53 8.1.2 Virtual RAM Boot.................................................................................................................53 8.1.3 Paged RAM Boot ................................................................................................................54 9. Design Considerations ...........................................................................................................55 9.1 General Guidelines ...........................................................................................................55 9.2 Configuration and GPIO Interface ....................................................................................55 9.3 Standard NOR-Like Interface ...........................................................................................56 9.4 Multiplexed Interface.........................................................................................................57 9.5 ...
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Standard Asynchronous Read Timing ................................................................................71 10.3.2 Standard Asynchronous Write Timing ................................................................................72 10.3.3 Multiplexed Asynchronous Read Timing.............................................................................73 10.3.4 Multiplexed Asynchronous Write Timing.............................................................................74 10.3.5 Standard Burst Read Timing...............................................................................................75 10.3.6 Standard Burst Write Timing ...............................................................................................76 10.3.7 Multiplexed Burst Read Timing ...........................................................................................77 10.3.8 ...
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... Theory of operation for the major building blocks Section 3: Data protection and security enabling features overview Section 4: Detailed description of modes of operation, including power failure management Section 5: and 128KByte memory window Embedded TrueFFS Technology overview Section 6: mDOC H3 register descriptions Section 7: Overview of how to boot from mDOC H3 ...
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... H3 is the latest addition to msystems’ mDOC product family. mDOC H3, packed in a small FBGA package and offering densities ranging from 1Gb (128MB) to 16Gb (2GB hybrid device with an embedded thin flash controller and high capacity flash memory. It uses the most advanced Flash technologies, enhanced by msystems’ proprietary TrueFFS embedded flash management software ...
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A 16-byte Unique ID (UID) identifies each device, eliminating the need for a separate ID device on the motherboard. A new 32-bit Random Number Generator (RNG) is also available. The RNG, in conjunction with ...
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Standard Interface 2.2.1 9x12/12x18 FBGA Ball Diagrams Figure 2 shows the mDOC H3 9x12mm/12x18mm 115 ball standard interface ball diagram. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should be connected as described ...
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FBGA Package RSRVD RSRVD D RSRVD RSRVD GPIO_ TIMER F RSRVD A 2 RSRVD RSRVD H RSRVD RSRVD RSRVD K ...
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... ST Write Enable, active low Configuration ST/PU GPIO or configurable timer. PD Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1: ID0 = VSS Chip 2: ID0 = VCCQ ST Lock, active low. When active, provides full hardware data protection of selected partitions. Control ST/PU Warm reset input, used for triggering device warm-reset ...
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Signal Type Signal Ball No. CLK L6 CMOS 3-STATE DMARQ# H8 CMOS 3-STATE Interrupt Request. Active low. If not used may IRQ# G9 ST/PU/CMOS 3- SCS# G10 ST/PU/CMOS 3- SO H10 ST/PU/CMOS 3- SI J10 ST/PU/CMOS 3- SCLK K10 VCC2 ...
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... The following abbreviations are used Schmidt Trigger input. IN/PD – CMOS input with internal pull down resistor (77KΩ to 312KΩ; 135KΩ typical), which is enabled only when 8KB memory window is in use, ST/PU - Schmitt Trigger input with internal pull up resistor (95KΩ ...
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System Interface See Figure 3 for a simplified I/O diagram for a standard interface of mDOC H3. For power connectivity please refer to mDOC H3 power supply connectivity in section 9.5. Figure 3: Standard Interface Simplified I/O Diagram 18 ...
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Multiplexed Interface 2.3.1 9x12/12x18 FBGA Ball Diagram Figure 4 shows the mDOC H3 9x12mm/12x18mm115 ball multiplexed interface ball diagram. To ensure proper device functionality, balls marked RSRVD are reserved for future use and should be connected as described in ...
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FBGA Package RSRVD RSRVD D RSRVD RSRVD E VSS GPIO _ TIMER F RSRVD VSS RSRVD VSS G A0 RSRVD H RSRVD RSRVD RSRVD K RSRVD RSRVD ...
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... ST/PU GPIO or configurable timer. ST/PU Address Valid strobe. Set multiplexed interface. PD Identification. Configuration control to support up to two chips cascaded in the same memory window. Chip 1: ID0 = VSS Chip 2: ID0 = VCCQ ST Lock. Active low. When active, provides full hardware data protection of selected partitions. ...
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Signal Type Signal Ball No. ST/PU/CMOS SCS# G10 ST/PU/CMOS SO H10 ST/PU/CMOS SI J10 ST/PU/CMOS SCLK K10 VCC2 D5 VCC1 E7 VCCQ K6, G4 VCC K5 VSS D3, D4, D7, D8, E2, E3, E4 E8, E10, F2, F3, F4, F7, ...
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... The following abbreviations are used Schmidt Trigger input. IN/PD – CMOS input with internal pull down resistor (77KΩ to 312KΩ; 135KΩ typical), which is enabled only when the 8KB memory window is in use, ST/PU - Schmitt Trigger input with internal pull up resistor (95KΩ ...
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System Interface See Figure 5 for a simplified I/O diagram of multiplexed interface mDOC H3. For power connectivity please refer to mDOC H3 power supply connectivity in section 9.5. Figure 5: Multiplexed Interface Simplified I/O Diagram 24 Data Sheet ...
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... Boot Agent – Management of host boot sequence – Loading of Boot code from flash media upon power up. • ECC / EDC - Error Detection and Error Correction Codes (EDC/ECC) - On-the-fly Flash error handling. • Data Buffer – 4KB DPRAM memory, used as a pipeline buffer, for enhanced data transfer rate. 25 Figure 6: Simplified Block Diagram Data Sheet (Preliminary) Rev ...
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... EEPROM-like interface enables direct access to the Programmable Boot Block to permit XIP (Execute-In-Place) functionality during system initialization. A1-A16 address lines enable access to the mDOC H3 128KB memory window. When migrating from mDOC G3/G4/H1 without changing the PCB, thus using only A1-A12 address lines, mDOC H3 exports 8KB memory window, like in mDOC G3/G4 and H1 ...
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Serial Interface The Serial interface (SPI) provides mDOC H3 a secondary interface with debug and programming capabilities. mDOC H3 SPI Interface is configured as Slave. All four combinations of clock phase (CPHA) and clock polarity (CPOL) defined by the ...
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H3 will respond only to accesses to the XIP Boot Block (including Paged or Virtual RAM accesses) in order to facilitate completion of the IPL execution. Once Embedded TrueFFS is loaded, executed and completed its media mount process, ...
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D P ATA ROTECTION AND 4.1.1 Read/Write-Protected partitions Data and code protection is implemented on a per-partition basis. The user can configure each partition as read protected, write protected, or read and write protected. A protected partition may be ...
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One-Time Programmable (OTP) Partitions OTP feature is implemented on a per-partition basis, for full flexibility. Once a partition has been defined as ...
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DOC ODES OF Figure 7 shows the different modes of mDOC H3 device operation and the interchange between optional modes. mDOC H3 can operate in any one of five basic power modes/states: • Reset state • ...
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... Power Save Mode This mode defined as a "work mode" and is optimized for balance between power consumption and performance. Balance is achieved by setting internal clocks to predefined optimal settings. In this mode all standard operations involving the flash memory can be performed. 5.4 Standby Mode mDOC H3 enters standby mode upon device inactivity. In Standby mode the clock of most internal cores is either disconnected or reduced to a minimum ...
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Entering Deep Power-Down mode and then returning to the previous mode does not affect the value of any register. Exiting Deep Power-Down mode is done using one of the following methods: • Performing a read/write access from/to mDOC H3 • ...
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... RUE 6.1 General Description msystems’ patented TrueFFS technology was designed to maximize the benefits of flash memory while overcoming inherent flash limitations that would otherwise reduce its performance, reliability and lifetime. TrueFFS emulates a hard disk making flash transactions completely transparent to the OS. In addition, since DOC driver operates under the OS file system layer, and exports standard Block Device API completely transparent to the application ...
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... Wear-Leveling Flash memory can be erased a limited number of times. This number is called the erase cycle limit, or write endurance limit, and is defined by the flash device vendor. The erase cycle limit applies to each individual erase block in the flash device. ...
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... This procedure serves as a check on data integrity. The “erase after write” algorithm is also used to update and store mapping information on the flash memory. This keeps the mapping information coherent even during power failures. The only mapping information held in RAM is a table pointing to the location of the actual mapping information ...
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The driver version can be verified by the sign-on messages displayed the version information presented by the driver or tool. 37 Data Sheet (Preliminary) Rev. 0.2 mDOC H3 Embedded Flash Drive 92-DS-1205-10 ...
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... Memory Window mDOC H3 driver utilizes a 128KB memory window in the CPU address space, consisting of four 32KB sections as depicted in Figure 8. The addresses described here are relative to the absolute starting address of the 128KB memory window. The 32KB Programmable Boot Block (XIP) is aliased to section 0, 2 and 3. The sections are aligned to addresses 00000H, 10000H and 18000H additionally the second half of section 1 contains the second half of the IPL ...
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... Memory Window For the purposes of backward compatibility, mDOC H3 can present an 8KB memory window in the CPU address space, depicted in Figure 9. The addresses described here are relative to the absolute starting address of the 8KB memory window. The 2KB Programmable Boot Block (XIP) in section 0 is aligned to address 0000H. ...
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DOC EGISTERS This section describes various mDOC H3 registers and their functions. Address (Hex) Address (Hex) 128KB Window 8KB Window 0030 0070 0080 800E 800E 801C 9400/9422 1400/1422 9402/9424 1402/1424 9404 9406 9408 940A 940C 9416 ...
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Reset Values The Reset value written in the register description is the register value after mDOC H3 moves out from Reset state and enters one of the Work modes. Registers for which a value is not defined after moving ...
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PAGE value of 00H loads the same data as in hardware or software reset. Note: This register cannot be accessed when the A0 signal is pulled high. Therefore it is recommended that A0 will be connected to Host CPU A0, ...
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Device Ready indication. DRDY 0: Device not ready 1: Device Ready Data Request. . DRQ 0: Not ready to transfer data. 1: Ready to transfer data. Error bit. ERR 0: No error has occurred error has occurred during ...
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Interrupt enable (to the host): 0: Interrupt enable 1: Interrupt Disable 7.3.7 Chip Identification (ID) Register [0:1] Description: These two 16-bit registers are used to identify the mDOC device residing on the host platform. They always return the same ...
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HOLD Specifies if the data output/input on D [15:0] during burst mode read/write cycles should be held for one or two clock cycle. 0: Data is held for one clock cycle. 1: Data is held for two clock cycles. LENGTH ...
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Note: 1. This register cannot be accessed when the A0 signal is pulled high. Therefore it is recommended that A0 will be connected to Host CPU A0 VSS. 2. Burst mode can only be used in conjunction with ...
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H3 internal RAM (Boot Block). 00: Whole XIP block is enabled. 01: Shut the lower the physical XIP block. 10: Shut the upper 16KB of the physical XIP block. 11: Shut the entire 32KB ...
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Note: This register cannot be accessed when the A0 signal is pulled high. Therefore it is recommended that A0 will be connected to Host CPU A0 VSS. 7.3.13 Power-Down Register Description: This 16-bit register controls the device response ...
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DMA Control Register Description: This 16-bit register controls the DMA_REQ signal to the host. Address (hex): 940E (128KB window) / 140E (8KB window) Type: Read / Write D15-D9 D8-D4 Bit number Read/Write R R/W RFU PULSE_WIDTH RFU Bit name ...
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D15-D10 Bit number Read/Write R Bit name RFU 0 Reset value DMA programmable negation: DMA_PROG_NEG 0-1023: Number of clocks before end of data transfer that DMARQ# signal will be negated. Note: DMA negation must be smaller than transfer size in ...
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Endian Control Register Description: This 16-bit register is used to control the swapping of the low and high data bytes when reading or writing with a 16-bit host. This provides an Endian- independent method of enabling/disabling the byte swap ...
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B DOC H3 OOTING FROM M 8.1 Introduction mDOC H3 can function both as a flash disk and as the system boot device. If mDOC H3 is used both as a flash disk and as the system boot device, ...
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Figure 10 illustrates an example of a boot sequence. Power-Up Boot Loader Basic System Initialization oot Loader Copies B OS Image to RAM OS Start-Up Code RAM OS Image Figure 10: System Boot Sequence with mDOC H3 8.1.1 Asynchronous Boot ...
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... When mDOC H3 is configured for Virtual RAM Boot mode, the mode is retained after Reset as well. While in this mode, read cycles from the entire mDOC H3 128KB memory window return virtual RAM data. Access to an address that is not within the physical window of this configuration (2KB in 8KB window or 32KB in 128KB window), initiates a download operation in which the required data is copied from the NAND flash to the physical SRAM ...
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... ONSIDERATIONS 9.1 General Guidelines • A typical RISC processor memory architecture may include the following devices: • mDOC H3: Contains the OS image, applications, registry entries, back-up data, user files and data, etc. It can also be used to perform boot operation, thereby replacing the need for a separate boot device. • ...
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... Standard NOR-Like Interface mDOC H3 uses a NOR-like interface that can easily be connected to any microprocessor bus. With a standard interface, it requires 16 address lines, 16 data lines and basic memory control signals (CE#, OE#, WE#), as shown in Figure 11 below. Typically, mDOC H3 can be mapped to any free 128KB memory space (8KB address space requires less address lines). ...
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Multiplexed Interface With multiplexed interface, mDOC H3 requires the signals shown in Figure 12 below. 0.1µF Address/Data bus Output enable Write enable Chip enable Address valid clock Reset Warm Reset ID For power connectivity please refer to mDOC H3 ...
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... OE# (Output Enable) and Write Enable (WE#) – Connect these signals to the host RD# and WR# signals, respectively. • CE# (Chip Enable) – Connect this signal to the memory address decoder. Most RISC/mobile processors include a programmable decoder to generate various Chip Select (CS) outputs for different memory zones. These CS signals can be programmed to support different wait states to accommodate mDOC H3 timing specifications. • ...
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BUSY# (Busy) – This signal indicates when the device is ready for first access after reset. It may be connected to an input port of the host, or alternatively it may be used to hold the host in a ...
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H3 will interrupt the host system in the following cases: • On completion of block device operation to mDOC H3. • Device is ready to send a data block during a read operation. • Device is ready to receive ...
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If host DMA controller detects the de-assertion of the DMARQ# signal too late (and attempts to transfer additional words as a result), then DMARQ# can be configured to be de- asserted earlier by using the DMA Negation Register. 5. ...
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Note: In Burst write the wait states start from the N The LATENCY field controls the number of clock cycles between mDOC H3 sampling CE# being asserted and when the first word of data is available to be latched by ...
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V SS CE# OE# WE# Figure 13: Standard Interface, Cascaded Configuration 9.10 Platform-Specific Issues This section discusses hardware design issues for major embedded RISC processor families. 9.10.1 Wait State Wait states can be implemented only when mDOC H3 is designed ...
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Note: mDOC H3 does NOT use this signal to indicate that the flash is in busy state (e.g. program, read, or erase). 9.10.4 Working with 16/32-Bit Systems mDOC H3 uses a 16-bit data bus and supports 16-bit data access by ...
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Note: The prefix “SA” indicates system host address lines Figure 17: Address Shift Configuration for 32-Bit Data Access Mode 9.11 Design Environment mDOC H3 provides a complete design environment consisting of: • Evaluation boards (EVBs) for enabling software integration and ...
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P S RODUCT PECIFICATIONS 10.1 Environmental Specifications 10.1.1 Operating Temperature Extended temperature range: -40°C to +85°C 10.1.2 Thermal Characteristics Junction to Case (θ * Note: Final numbers may vary within a range of 10% 10.1.3 Humidity 10% to 90% ...
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DC Characteristics 10.2.3.1 1.8V Core, 1.8V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply VIH Input High-level Voltage VIL Input Low-level Voltage II Input Leakage Current IOZ Tri-State output leakage current ...
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Core, 1.8V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply Input High-level Voltage VIH Input Low-level Voltage VIL II Input Leakage Current IOZ Tri-State output leakage current Hysteresis Vhys High-level ...
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Core, 3.3V I/O Symbol Parameter VCCQ I/O power supply VCC2 Internal supply VCC Device supply VCC1 Internal supply VIH Input High-level Voltage VIL Input Low-level Voltage II Input Leakage Current IOZ Tri-State output leakage current Vhys Hysteresis VOH ...
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Parameter Push/Pull outputs 70 1.8V 30pF Data Sheet (Preliminary) Rev. 0.2 mDOC H3 Embedded Flash Drive 3.3V 30pF 92-DS-1205-10 ...
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Timing Specifications 10.3.1 Standard Asynchronous Read Timing Figure 18: Standard Asynchronous Read Timing CE OE Tsua Address Data Figure 19: Standard Read Timing – Asynchronous Boot Mode Table 12: Standard Asynchronous Read Timing Parameters Symbol Address setup time (Figure ...
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Standard Asynchronous Write Timing CE WE Address Data Figure 20: Standard Asynchronous Write Timing Table 13: Standard Asynchronous Write Timing Parameters Symbol Tasu (regs) Address setup (Registers) Tah Address hold time Tdsu Data setup Tdh Data hold Tw(ceh) WE# ...
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Multiplexed Asynchronous Read Timing CE OE Tavd Tavd AVD Tasu Data Address valid Figure 21: Multiplexed Asynchronous Read Timing Diagram Table 14: Multiplexed Asynchronous Read Timing Parameters Symbol Tasu Address setup Tah Address hold Taccs Access time Tdh Data ...
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Multiplexed Asynchronous Write Timing CE WE Tavd Tavd AVD Tah Tasu Data A0 Figure 22: Multiplexed Asynchronous Write Timing Diagram Table 15: Multiplexed Asynchronous Write Timing Parameters Symbol Tasu Address setup Tah Address hold Tdsu Data setup time Tdh ...
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Standard Burst Read Timing Bur s t_c lk CLK Tah Tas u A ddres Data Figure 23: Standard Burst Read Timing Diagram Table 16: Standard Burst Read Timing Parameters Symbol Tasu ...
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Standard Burst Write Timing Burst CLK Tcesu CE Tah Tasu Address A0 Tweh Twesu WE Data Figure 24: Standard Burst Write Timing Diagram Table 17: Standard Burst Write Timing Parameters Symbol Tasu Address setup Tah Address hold Tcesu CE# ...
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Multiplexed Burst Read Timing Burst CLK Tcesu CE OE Tavdh Tavdsu AVD Tdsu Tdh Data Valid add Figure 25: Multiplexed Burst Read Timing Diagram Table 18: Multiplexed Burst Read Timing Parameters Symbol Tasu Address setup Tah Address hold Tcesu ...
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DMA Request Timing Diagram 10.3.8.1 Asynchronous Data Transfer Table 19 lists DMA request timing parameters and Figure 26 shows the DMA request timing diagram in Asynchronous data transfer. CE DMARQ# Figure 26: DMA Request Timing Diagram (Asynchronous Data Transfer) ...
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SPI Timing Table 21 lists SPI slave timing parameters. Figure 28 and Figure 29 show the SPI slave timing diagram. Symbol Description tw(SCLK1) SCK high pulse width tw(SCLK0) SCK low pulse width tcyc(SCLK) SCK period tsu(SI SCLK ...
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... Power-Up Timing mDOC H3 is reset by assertion of the RSTIN# input. When this signal is negated, mDOC H3 initiates a download procedure from the flash memory into the internal Programmable Boot Block. During this procedure, mDOC H3 does not respond to read or write access. Host systems must therefore observe the requirements described below for initial access to mDOC H3 ...
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Symbol T (VCC-RSTIN) VCC/VCCQ stable to RSTIN# REC T (RSTIN) RSTIN# asserted pulse width W T (BUSY0) RSTIN (BUSY1) RSTIN (VCC-BUSY0) VCC/VCCQ stable to BUSY Tsu (RSTIN-AVD) RSTIN (RSTIN-D) RSTIN# Trise (RSTIN) ...
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Mechanical Dimensions 10.4.1 mDOC H3 1Gb (128MB)/2Gb (256MB) FBGA 128MB (1Gb) dimensions: 9.0 ±0. 12.0 ±0. 1.1 ±0.1 mm Ball pitch: 0.8 mm 9.0 0. INDEX 4X 0.15 Top Figure 31: Mechanical Dimensions ...
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H3 4Gb (512MB)/8Gb (1GB)/ 16Gb (2GB) FBGA dimensions: 12.0 ±0. 18.0 ±0. 1.3 ±0.1 mm Ball pitch: 0.8 mm 12.0 INDEX Top Figure 32: Mechanical Dimensions 12x18 FBGA Package 83 1.3±0.1 2.4 0.26±0.04 P ...
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... O I RDERING NFORMATION See Table 23 for mDOC H3 devices available and the associated order information. Ordering Code MD2534-d1G-X-P MD2534-d2G-X-P MD2533-d8G-X-P MD2533-d16G-X-P 84 Table 23: mDOC H3 Order information Capacity Package MB Mb 1024 9x12 BGA 128 (1Gbit) 115 balls 2048 9x12 BGA 256 (2Gbit) 115 balls 12x18 ...
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ONTACT S USA M-Systems, Inc. 555 North Mathilda Avenue, Suite 220 Sunnyvale, CA 94085 Phone: +1-408-470-4440 Fax: +1-408-470-4470 Japan M-Systems Japan Inc. Asahi Seimei Gotanda Bldg., 3F 5-25-16 Higashi-Gotanda Shinagawa-ku Tokyo, 141-0022 Phone: +81-3-5423-8101 Fax: ...