MD8331-D2G-V18-X-P SanDisk, MD8331-D2G-V18-X-P Datasheet - Page 23

• Manufacturer Part Number: MD8331-D2G-V18-X-P
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V18-X-P

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1150-2; MD8831-D2G-V18-X-P; MD8832-D2G-V18-X-P

During the download process, DiskOnChip G4 asserts the BUSY# signal to indicate to the system
that it is not yet ready to be accessed. Once BUSY# is negated, the system can access
DiskOnChip G4.
A failsafe mechanism prevents improper initialization due to a faulty VCC or invalid assertion of
the RSTIN# input. Another failsafe mechanism is designed to overcome possible NAND flash data
errors. It prevents internal registers from powering up in a state that bypasses the intended data
protection. In addition, any attempt to sabotage the data structures causes the entire DiskOnChip to
become both read and write protected, and completely inaccessible.
3.7
Because NAND-based MLC flash is prone to errors, it requires unique error-handling capability. M-
Systems’ x2 technology implements 4-bit Error Detection Code/Error Correction Code (EDC/ECC),
based on a patented combination of Bose, Chaudhuri and Hocquenghem (BCH) and Hamming code
algorithms. Error Detection Code (EDC) is implemented in hardware to optimize performance,
while Error Correction Code (ECC) is performed in software, when required, to save silicon costs.
Each time a 512-byte page is written, additional parity bits are calculated and written to the flash.
Each time data is read from the flash, the parity bits are read and used to calculate error locations.
The Hamming code can detect 2 errors per page and correct 1 error per page. The BCH code can
detect and correct 4 errors per page. It can even detect 5 errors per page with a probability of 99.9%.
It ensures that the minimal amount of code required is used for detection and correction to deliver
the required reliability without degrading performance.
3.8
The Control and Status block contains registers responsible for transferring address, data and
control information between the DiskOnChip TrueFFS driver and the flash media. Additional
registers are used to monitor the status of the flash media (ready/busy) and the DiskOnChip
controller. For further information on the DiskOnChip registers, refer to Section 7.
3.9
DiskOnChip G4 128MB (1Gb) consists of one 128MB (1Gb) flash planes that consist of 512
blocks, organized in 128 pages, as follows:
23
• Page – Each page contains 2048 bytes of user data and a 64-byte extra area that is used to
• Block (Erase Unit) – Each block contains 128 pages (total of 256KB), as shown in Figure
Error Detection Code/Error Correction Code (EDC/ECC)
Control and Status
store flash management and EDC/ECC signature data, as shown in Figure 6.
7. A block is the minimal unit that can be erased, and is sometimes referred to as an erase
block.
Flash Architecture
512 Bytes
Data Sheet (Preliminary) Rev. 0.3
User Data
16 Bytes
Flash Management &
ECC/EDC Signature
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
2 KB
92-DS-1105-00