EPC4QI100 Altera, EPC4QI100 Datasheet - Page 58

• Manufacturer Part Number: EPC4QI100
• Description: IC CONFIG DEVICE 4MBIT 100-PQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC4QI100

• Programmable Type: In System Programmable
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-2189

3–6
Figure 3–4. Multiple Devices in AS Mode
Notes to
(1) For the V
(2) Serial configuration devices cannot be cascaded.
(3) Connect the FPGA MSEL[] input pins to select the AS configuration mode. For details, refer to the appropriate FPGA family chapter in the
(4) Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate FPGA family chapter in the
(5) For more information about configuration pin I/O requirements in an AS scheme for an Altera FPGA, refer to the respective FPGA family handbook
Configuration Handbook (Complete Two-Volume Set)
Configuration
Configuration
Configuration chapter.
Figure
CC
value, refer to the respective FPGA family handbook Configuration chapter.
3–4:
Configuration
Device (2)
Handbook.
Handbook.
Serial
DATA
DCLK
ASDI
nCS
Multiple devices can be configured by a single EPCS device. However, serial
configuration devices cannot be cascaded. Refer to
programming file size of the cascaded FPGAs does not exceed the capacity of a serial
configuration device.
FPGAs in the chain. The first FPGA is the configuration master and has its MSEL[]
pins set to AS mode. The following FPGAs are configuration slave devices and have
their MSEL[] pins set to PS mode.
Chapter 3: Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
(Note
1),
CONF_DONE
nSTATUS
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
Figure 3–4
Altera FPGA (Master)
(5)
V
CC
10 k
(1)
V
CC
shows the AS configuration scheme with multiple
MSEL[]
10 k
(1)
nCEO
V
CC
10 k
(3)
(1)
Table 3–1
CONF_DONE
nSTATUS
nCONFIG
nCE
DATA0
DCLK
Altera FPGA (Slave)
© December 2009
to ensure the
Active Serial FPGA Configuration
MSEL[ ]
nCEO
N.C.
(4)
Altera Corporation