EPC2TI32N Altera, EPC2TI32N Datasheet

IC CONFIG DEVICE 1.6MBIT 32-TQFP

EPC2TI32N

Manufacturer Part Number
EPC2TI32N
Description
IC CONFIG DEVICE 1.6MBIT 32-TQFP
Manufacturer
Altera
Series
EPCr
Datasheet

Specifications of EPC2TI32N

Programmable Type
In System Programmable
Memory Size
1.6Mb
Voltage - Supply
3 V ~ 3.6 V, 4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1648

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Features
© December 2009
CF52005-2.4
f
f
Altera Corporation
This chapter describes configuration devices for SRAM-based LUT Devices.
For detailed information about enhanced configuration devices, refer to
Configuration Devices (EPC4, EPC8 and EPC16) Data
For detailed information about serial configuration devices, refer to
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64 and EPCS128) Data
Configuration device family for configuring Altera
(including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria
Cyclone
Mercury
Easy-to-use 4-pin interface to Altera FPGAs
Low current during configuration and near-zero standby current
5.0-V and 3.3-V operation
Programming support with the Altera Programming Unit (APU) and
programming hardware from Data I/O, BP Microsystems, and other third-party
programmers
Available in compact plastic packages
EPC2 device has reprogrammable Flash configuration memory
8-pin plastic dual in-line package (PDIP)
20-pin plastic J-lead chip carrier (PLCC) package
32-pin plastic thin quad flat pack (TQFP) package
5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std.
1149.1
Supports programming through Serial Vector Format Files (.svf), Jam
Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL
Byte-Code Files (.jbc), and the Quartus
the USB Blaster, MasterBlaster
ByteBlasterMV
nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA
configuration
Can be programmed with Programmer Object Files (.pof) for EPC1 and
EPC1441 devices
Available in 20-pin PLCC and 32-pin TQFP packages
®
, Cyclone II, FLEX
, Stratix
4. Configuration Devices for SRAM-Based
®
, Stratix GX, Stratix II, and Stratix II GX devices.
download cable
®
10K (including FLEX 10KE and FLEX 10KA)
, ByteBlaster
®
II and MAX+PLUS
Configuration Handbook (Complete Two-Volume Set)
LUT Devices Data Sheet
Sheet.
II, EthernetBlaster, or
®
ACEX
®
1K, APEX
®
Serial
II softwares via
®
Enhanced
GX,
Sheet.
20K

EPC2TI32N Summary of contents

Page 1

... Easy-to-use 4-pin interface to Altera FPGAs ■ Low current during configuration and near-zero standby current ■ 5.0-V and 3.3-V operation Programming support with the Altera Programming Unit (APU) and ■ programming hardware from Data I/O, BP Microsystems, and other third-party programmers ■ Available in compact plastic packages 8-pin plastic dual in-line package (PDIP) ■ ...

Page 2

... Functional Description With SRAM-based devices, configuration data must be reloaded each time the device powers up, the system initializes, or when new configuration data is needed. Altera configuration devices store configuration data for SRAM-based ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices ...

Page 3

... EP2C70 FLEX 10K EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 FLEX 10KA EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A © December 2009 Altera Corporation Data Size (Bits) EPC1064/ (1) 1064V EPC1213 354,832 — — 648,016 — — 1,008,016 — — 1,524,016 — — ...

Page 4

... December 2009 Altera Corporation ...

Page 5

... DCLK nCS OE Notes to Figure 4–1: (1) The EPC1441 devices do not support data cascading. The EPC1, EPC2, and EPC1213 devices support data cascading. (2) The OE pin is a bidirectional open-drain pin. © December 2009 Altera Corporation Data Size (Bits) EPC1064/ (1) 1064V EPC1213 5,000,000 — — ...

Page 6

... Altera FPGA. For specific details about configuration interface connections, including pull-up resistor values, supply voltages and MSEL pin setting, refer to the appropriate FPGA family chapter in the Handbook. Figure 4–2. Altera FPGA Configured Using an EPC1, EPC2, or EPC1441 Configuration Device FPGA CONF_DONE n ...

Page 7

... DATA, and OE) are connected to every device in the chain. Figure 4–3 shows the basic configuration interface connections between a configuration device chain and the Altera FPGA. f For specific details about configuration interface connections, including pull-up resistor values, supply voltages and MSEL pin setting, refer to the appropriate FPGA family chapter in the © ...

Page 8

... Configuration Devices for SRAM-Based LUT Devices Data Sheet Figure 4–3. Altera FPGA Configured Using Two EPC1 or EPC2 Configuration Devices ...

Page 9

... MAX+PLUS II software’s Global Project Device Options dialog box (Assign menu). f For more information about FPGA configuration and configuration interface connections between configuration devices and Altera FPGAs, refer to the appropriate FPGA family chapter in the Power and Operation This section describes Power-On Reset (POR) delay, error detection, and 3.3-V and 5 ...

Page 10

... This low signal on nSTATUS will drive the OE pin of the configuration device low, which will reset the configuration device. CRC checking is performed when configuring all Altera FPGAs. 3.3-V or 5.0-V Operation The EPC1, EPC2, and EPC 1441 configuration device may be powered at 3 ...

Page 11

... CONF_DONE pull-up resistors must be connected to 3 these configuration devices are powered at 5.0 V, the nSTATUS and CONF_DONE pull-up resistors can be connected to 3 5.0 V. © December 2009 Altera Corporation , while a low logic level means the pin should be CC VPP Voltage Level VCCSEL Pin Logic (V) 3 ...

Page 12

... Configuration Devices for SRAM-Based LUT Devices Data Sheet Programming and Configuration File Support The Quartus II and MAX+PLUS II softwares provide programming support for Altera configuration devices. During compilation, the Quartus II and MAX+PLUS II softwares automatically generates a ...

Page 13

... Device EPC2 EPC1 EPC1441 The following steps explain how to program Altera configuration devices using the Quartus II software and the APU: 1. Choose the Quartus II Programmer (Tools menu). 2. Load the appropriate .pof by clicking Add. The Device column displays the device for the current programming file. ...

Page 14

... These instructions are used when programming an EPC2 device via JTAG ports with a USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlaster MV download cable, or using a .jam, .jbc, or .svf via an embedded processor. Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan or the EPC2 BSDL files on the Altera web site. .pof , .jam, .jbc) in © December 2009 Altera Corporation ...

Page 15

... Capture register setup time JSSU t Capture register hold time JSH t Update register clock to output JSCO t Update register high-impedance to valid JSZX output t Update register valid output to high JSXZ impedance © December 2009 Altera Corporation t JCP JCH JCL JPSU t t JPZX JPCO t t JSSU ...

Page 16

... MHz 40 65 100 100 ns 40 — — — — ns — — — — 100 — — ns — — — — © December 2009 Altera Corporation ...

Page 17

... DCLK frequency CLK t DCLK high time for the first device in the configuration MCH chain t DCLK low time for the first device in the configuration MCL chain © December 2009 Altera Corporation Min Typ Max — — 200 — — 80 — — 300 30 — ...

Page 18

... December 2009 Timing Information Max Units — ns — — EPC1 Max Unit — ns — ns — ns — — MHz — ns — — 100 ns Altera Corporation ...

Page 19

... CMOS output voltage V Low-level output voltage OL I Input leakage current I I Tri-state output off-state current OZ © December 2009 Altera Corporation Table 4–19 provide information about absolute maximum ratings, (Note 1) Conditions With respect to ground (2) With respect to ground (2) — — — ...

Page 20

... Table 4–19: (1) For more information, refer to the Operating Requirements for Altera Devices Data Sheet. (2) The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2 overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns under no-load conditions. ...

Page 21

... DATA 2 4 DCLK © December 2009 Altera Corporation 32-Pin TQFP (2) Pin Type 31 Output Serial data output. The DATA pin connects to the DATA0 of the FPGA. DATA is latched into the FPGA on the rising edge of DCLK. The DATA pin is tri-stated before configuration and when the nCS pin is high ...

Page 22

... JTAG data input pin. Connect this pin to V JTAG circuitry is not used. This pin is only available in EPC2 devices. 28 Output JTAG data output pin. Do not connect this pin if the JTAG circuitry is not used. This pin is only available in EPC2 devices. Pin Information Description if the CC © December 2009 Altera Corporation ...

Page 23

... Notes to Table 4–20: (1) This package is available for EPC1 and EPC1441 devices only. (2) This package is available for EPC2 and EPC1441 devices only. © December 2009 Altera Corporation 32-Pin TQFP (2) Pin Type 25 Input JTAG mode select pin. Connect this pin to V JTAG circuitry is not used. ...

Page 24

... Package (Note N.C. N. VCC 2 22 N.C. N. N.C. N. N.C. N. N.C. N. N. 32-Pin TQFP EPC1441 EPC1064 EPC1064V nCASC is a reserved pin and should N.C. VPP 23 N.C. 22 N.C. 21 N.C. 20 N.C. 19 N.C. 18 VPPSEL Altera Device Package Information © December 2009 Altera Corporation ...

Page 25

... April 2007 2.2 ■ July 2004 2.0 ■ September 2003 1.0 ■ © December 2009 Altera Corporation Package Temperature 32-pin TQFP 32-pin TQFP 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 8-pin PDIP 8-pin PDIP 32-pin TQFP 32-pin TQFP ...

Page 26

... Configuration Devices for SRAM-Based LUT Devices Data Sheet Configuration Handbook (Complete Two-Volume Set) Chapter Revision History © December 2009 Altera Corporation ...

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