EPC2TI32N Altera, EPC2TI32N Datasheet - Page 7

• Manufacturer Part Number: EPC2TI32N
• Description: IC CONFIG DEVICE 1.6MBIT 32-TQFP
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC2TI32N

• Programmable Type: In System Programmable
• Memory Size: 1.6Mb
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1648

Chapter 4: Configuration Devices for SRAM-Based LUT Devices Data Sheet
Device Configuration
© December 2009
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Altera Corporation
FPGA will reset the device. When the JTAG state machine exits this state,
nINIT_CONF is released and pulled high by an internal 1-k resistor, which in turn
pulls nCONFIG high to begin configuration. If its functionality is not used, the
nINIT_CONF pin does not need to be connected and nCONFIG of the FPGA must be
pulled to V
The EPC2 device’s OE and nCS pins have internal programmable pull-up resistors. If
internal pull-up resistors are used, external pull-up resistors should not be used on
these pins. The internal pull-up resistors are used by default in the Quartus II
software. To turn off the internal pull-up resistors, check the Disable nCS and OE
pull-ups on configuration device option when generating programming files.
The configuration device’s OE and nCS pins control the tri-state buffer on its DATA
output pin, and enable the address counter and oscillator. When OE is driven low, the
configuration device resets the address counter and tri-states its DATA pin. The nCS
pin controls the DATA output of the configuration device. If nCS is held high after the
OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. If nCS is
driven low after the OE reset pulse, the counter and DATA output pin are enabled.
When OE is driven low again, the address counter is reset and the DATA output pin is
tri-stated, regardless of the state of nCS.
If the FPGA’s configuration data exceeds the capacity of a single EPC1 or EPC2
configuration device, multiple EPC1 or EPC2 devices can be cascaded together. If
multiple EPC1 or EPC2 devices are required, the nCASC and nCS pins provide
handshaking between the configuration devices.
EPC1441 and EPC1064/V devices cannot be cascaded.
When configuring ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II,
FLEX 10K, Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices with
cascaded EPC1 or EPC2 devices, the position of the EPC1 or EPC2 device in the chain
determines its mode of operation. The first configuration device in the chain is the
master, while subsequent configuration devices are slaves. The nINIT_CONF pin of
the master EPC2 device can be connected to the nCONFIG of the FPGAs, which allows
the INIT_CONF JTAG instruction to begin FPGA configuration. The nCS pin of the
master configuration device is connected to the CONF_DONE of the FPGAs, while its
nCASC pin is connected to nCS of the next slave configuration device in the chain.
Additional EPC1 or EPC2 devices can be chained together by connecting nCASC to
nCS of the next slave EPC1 or EPC2 device in the chain. The last device’s nCS input
comes from the previous device, while its nCASC pin is left floating. All other
configuration pins (DCLK, DATA, and OE) are connected to every device in the chain.
Figure 4–3
configuration device chain and the Altera FPGA.
For specific details about configuration interface connections, including pull-up
resistor values, supply voltages and MSEL pin setting, refer to the appropriate FPGA
family chapter in the
shows the basic configuration interface connections between a
CC
either directly or through a resistor.
Configuration
Handbook.
Configuration Handbook (Complete Two-Volume Set)
4–7