PCF8566P,112 NXP Semiconductors, PCF8566P,112 Datasheet - Page 20

• Manufacturer Part Number: PCF8566P,112
• Description: IC LCD DVR UNVRSL LOW-MUX 40-DIP
• Manufacturer: NXP Semiconductors

Specifications of PCF8566P,112

• Package / Case: 40-DIP (0.600", 15.24mm)
• Display Type: LCD
• Configuration: 7 Segment + DP, 14 Segment (24 Segment)
• Interface: I²C
• Current - Supply: 30µA
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Number Of Digits: 12
• Number Of Segments: 96
• Maximum Clock Frequency: 315 KHz
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 90 uA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1069-5; 933865310112; PCF8566PN

NXP Semiconductors
8. Basic architecture
PCF8566_7
Product data sheet
8.1.1 Bit transfer
8.1 Characteristics of the I
Table 7.
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blinking
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (see
The I
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in
Blinking mode
off
1
2
3
Fig 12. Bit transfer
2
C-bus provides bidirectional, two-line communication between different IC or
Blink frequencies
SDA
SCL
Rev. 07 — 25 February 2009
Normal operating
mode ratio
-
f
f
f
blink
blink
blink
=
=
=
2
C-bus
--------------- -
92160
------------------- -
184320
------------------- -
368640
f
f
f
clk
clk
clk
data valid
data line
stable;
Table
Universal LCD driver for low multiplex rates
9).
Power saving mode
ratio
-
f
f
f
change
allowed
of data
blink
blink
blink
=
=
=
--------------- -
15360
--------------- -
30720
--------------- -
61440
f
f
f
elk
clk
clk
Figure
mba607
Blink frequency
blinking off
2 Hz
1 Hz
0.5 Hz
12.
PCF8566
© NXP B.V. 2009. All rights reserved.
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