ADE7878ACPZ Analog Devices Inc, ADE7878ACPZ Datasheet - Page 66

• Manufacturer Part Number: ADE7878ACPZ
• Description: IC ENERGY METERING 3PH 40LFCSP
• Manufacturer: Analog Devices Inc

Specifications of ADE7878ACPZ

• Input Impedance: 400 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.4V
• Current - Supply: 22mA
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-WFQFN, CSP Exposed Pad
• Meter Type: 3 Phase
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LFCSP
• No. Of Pins: 40
• Msl: MSL 1 - Unlimited
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADE7878
HSDC is an interface that is used to send to an external device,
usually a microprocessor or a DSP, up to sixteen 32-bit words.
The words represent the instantaneous values of the phase currents
and voltages, neutral current, and active, reactive, and apparent
powers. The registers being transmitted are: IAWV[23:0],
VAWV[23:0], IBWV[23:0], VBWV[23:0], ICWV[23:0],
VCWV[23:0], AVA[23:0], INWV[23:0], BVA[23:0], CVA[23:0],
AWATT[23:0], BWATT[23:0], CWATT[23:0], AVAR[23:0],
BVAR[23:0], and CVAR[23:0]. All are 24-bit registers that are
sign extended to 32-bits (see Figure 34 for details). HSDC can
be interfaced with SPI or similar interfaces.
HSDC is always a master of the communication and consists of
three pins: HSA, HSD, and HSCLK. HSA represents the select
signal. It stays active low or high when a word is transmitted
and is usually connected to the select pin of the slave. HSD is
used to send data to the slave and is usually connected to the
data input pin of the slave. HSCLK is the serial clock line. It is
generated by the ADE7878 and is usually connected to the serial
clock input of the slave. Figure 85 presents the connections
between the ADE7878 HSDC and slave devices containing an
SPI interface.
The HSDC communication is managed by the HSDC_CFG[7:0]
register (see Table 22). It is recommended to set the HSDC_CFG
register to the desired value before enabling the port using Bit 6
(HSDCEN) in the CONFIG[15:0] register. In this way, the state of
various pins belonging to the HSDC port do not take levels incon-
sistent with the desired HSDC behavior. After a hardware reset
or after power-up, the MISO/HSD and SS /HSA pins are set high.
Bit 0 (HCLK) in the HSDC_CFG[7:0] register determines the
serial clock frequency of the HSDC communication. When
SCLK
SCLK
MOSI
MISO
MOSI
SS
SS
0
0
0
0
Figure 84. SPI Write Operation of a 32-Bit Register
Figure 83. SPI Read Operation of a 32-Bit Register
0
0
0
0
0 0 0
0 0 0 0
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1
15 14
REGISTER ADDRESS
15 14
REGISTER ADDRESS
HCLK is 0 (the default value), the clock frequency is 8 MHz.
When HCLK is 1, the clock frequency is 4 MHz. A bit of data is
transmitted for every HSCLK high-to-low transition. The slave
device that receives data from HSDC samples the HSD line on
the low-to-high transition of HSCLK.
The words can be transmitted as 32-bit packages or as 8-bit
packages. When Bit 1 (HSIZE) in the HSDC_CFG[7:0] register is 0
(the default value), the words are transmitted as 32-bit packages.
When Bit HSIZE is 1, the registers are transmitted as 8-bit pack-
ages. The HSDC interface transmits the words MSB first.
Bit 2 (HGAP) introduces a gap of seven HSCLK cycles between
packages, when Bit 2 (HGAP) is set to 1. When Bit HGAP is
cleared to 0 (the default value), no gap is introduced between
packages and the communication time is shortest. In this case,
HSIZE does not have any influence on the communication, and
a bit is put on the HSD line every HSCLK high-to-low transition.
Bits[4:3] (HXFER[1:0]) decide how many words are
transmitted. When HXFER[1:0] is 00, the default value, then all
16 words are transmitted. When HXFER[1:0] is 01, only the
words representing the instantaneous values of the phase and
neutral currents and phase voltages are transmitted in the
following order: IAWV, VAWV, IBWV, VBWV, ICWV, VCWV,
and one 32-bit word that is always equal to INWV.
1 0
1 0 31 30
31 30
REGISTER VALUE
REGISTER VALUE
Figure 85. Connecting the ADE7878 HSDC with an SPI
ADE7878
1 0
1 0
HSCLK
HSD
HSA
MOSI
SCK
SS
SPI DEVICE