ADE7754ARRL Analog Devices Inc, ADE7754ARRL Datasheet
ADE7754ARRL
Specifications of ADE7754ARRL
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ADE7754ARRL Summary of contents
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FEATURES High Accuracy, Supports IEC 687/61036 Compatible with 3-Phase/3-Wire, 3-Phase/4-Wire and any Type of 3-Phase Services Less than 0.1% Error in Active Power Measurement over a Dynamic Range of 1000 to 1 Supplies Active Energy, Apparent Energy, Voltage RMS, Current ...
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ADE7754 Contents GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 FEATURES . . . . . . . . . ...
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ADE7754–SPECIFICATIONS Parameters ACCURACY Active Power Measurement Error Phase Error between Channels (PF = 0.8 Capacitive) (PF = 0.5 Inductive Power Supply Rejection Output Frequency Variation 1 DC Power Supply Rejection Output Frequency Variation Active Power Measurement Bandwidth V ...
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ADE7754 TIMING CHARACTERISTICS Parameter Spec Write Timing 400 100 8 Read Timing ...
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... Digital Output Voltage to DGND . . –0 Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Model ADE7754AR ADE7754ARRL EVAL-ADE7754EB *RW = Small Outline (Wide Body Package in Tubes) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7754 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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ADE7754 Pin No. Mnemonic Description Digital Power Supply. The supply voltage should be maintained ± 5% for specified operation This pin should be decoupled to DGND with a 10 µF capacitor in parallel with ...
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WYE CONNECTION GAIN = 1 0. INTERNAL REFERENCE 0.30 PHASE B 0.20 0.10 0.00 PHASE A PHASE C –0.10 –0.20 –0.30 –0.40 –0.50 0.01 0.1 1 CURRENT (% fs) TPC 1. Real Power Error as a ...
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ADE7754 1.00 GAIN = 1 0.80 INTERNAL REFERENCE 0.60 0. 0.20 0.00 –0. 0.5 –0.40 –0.60 –0.80 –1. FREQUENCY (Hz) TPC 7. Real Power Error as a Percentage of Read- ing over ...
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TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7754 is defined by the formula = Percentage Error − Energy Re gistered by ADE 7754 True Energy Phase Error Between Channels The HPF ...
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ADE7754 Figure 6 shows how the gain settings in PGA 1 (current channel) and PGA 2 (voltage channel) are selected by various bits in the gain register. The no-load threshold and sum of the absolute value can also be selected ...
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ALIASING EFFECTS IMAGE FREQUENCIES 0 2 417 FREQUENCY (kHz) Figure 9. ADC and Signal Processing in Current Channel or Voltage Channel CURRENT CHANNEL ADC Figure 10 shows the ADC and signal processing chain for the input IA of the current ...
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ADE7754 VOLTAGE CHANNEL ADC Figure 12 shows the ADC and signal processing chain for the input VA in voltage channel (which is the same for VB and VC GAIN[6: –100% TO +100 ...
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In addition to the enable bits, the zero-crossing detection interrupt of each phase is enabled/disabled by setting the ZXSEL bits of the MMODE register (Address 0Bh) to Logic respectively. Zero-Crossing Timeout Each zero-crossing detection has an associated ...
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ADE7754 VPEAK[7:0] PKV INTERRUPT FLAG (BIT C OF STATUS REGISTER) READ RSTATUS REGISTER Figure 17. Peak Detection Bits 2 and 3 of the measurement mode register define the phase supporting the peak ...
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The ADE7754 provides a means of digitally calibrating these small phase errors. The ADE7754 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for ...
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ADE7754 pattern. Current rms measurements of Phase A are corrupted by the signal on the Phase C current input, current rms measure- ments of Phase B are corrupted by the signal on the Phase A current input, and current rms ...
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If the VGAIN registers are used for apparent power calibration (WATMOD bits in VAMODE register = 1 or 2), the voltage rms values are changed by voltage gain register value as described in the expression = Voltage rms register ...
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ADE7754 I HPF CURRENT SIGNAL – i(t) –100% TO +100% FS 28F5C2h 00h 1V/GAIN1 D70A3Eh 1 V VOLTAGE SIGNAL – v(t) –100 100% FS 28F5h 00h 1V/GAIN2 D70Bh Figure 24 shows the signal processing in each phase for ...
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HPF PHASE A AAPGAIN HPF PHASE B BAPGAIN HPF PHASE C CAPGAIN V C Figure 26. Total Active Power Consumption Calculation For ...
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ADE7754 The discrete time sample period (T) for the accumulation register in the ADE7754 is 0.4 µs (4/10 MHz). In addition to calculating the energy, this integration removes any sinusoidal component that may be in the active power signal. Figure ...
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ACTIVE POWER PHASE ACTIVE POWER DFC PHASE ACTIVE POWER TOTAL ACTIVE POWER PHASE C Figure 29. ADE7754 Energy to Frequency Conversion A digital to frequency converter (DFC) is used to generate the CF pulsed ...
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ADE7754 by setting to Logic 1 Bit 3 of the gain register (Address 18h). See Table X. Any load generating an active power amplitude lower than the minimum amplitude specified will not be taken into account when accumulating the active ...
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Thus the IRQ line can also be used to signal the end of a cali- bration. Equation 14 is derived from Equations 8 and 12. ∫ × ∫ ...
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ADE7754 –89 I MULTIPLIER HPF 24 1 INSTANTANEOUS REACTIVE V POWER SIGNAL – p(t) Figure 32. Reactive Power Signal Processing TOTAL REACTIVE POWER CALCULATION The sum of the reactive powers coming from each phase gives the total reactive power consumption. ...
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See the Current RMS Calculation and Voltage RMS Calculation sections. Only the effect of the apparent power gain is shown on Figure 35. The minimum output range is given when the apparent power gain register content ...
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ADE7754 APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. = ∫ Apparent Energy Apparent Power t dt The ADE7754 achieves the integration of the apparent power signal by continuously accumulating the apparent power ...
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MMODE REGISTER BIT 4 FROM VA ZERO-CROSS ADC DETECT LPF1 MMODE REGISTER BIT 5 FROM VB ZERO-CROSS ADC DETECT LPF1 MMODE REGISTER BIT 6 FROM VC ZERO-CROSS ADC DETECT LPF1 The number of half line cycles is specified in the ...
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ADE7754 SERIAL INTERFACE ADE7754 has a built-in SPI interface. The serial interface of the ADE7754 is made of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input, which ...
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SCLK DIN COMMAND BYTE SCLK X X DIN MOST SIGNIFICANT BYTE Serial Read Operation During a data read operation from the ADE7754, data is shifted out at the ...
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ADE7754 INTERRUPTS ADE7754 interrupts are managed through the interrupt status register (STATUS[15:0], Address 10h) and the interrupt enable register (IRQEN[15:0], Address 0Fh). When an interrupt event occurs in the ADE7754, the corresponding flag in the interrupt status register is set ...
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ACCESSING THE ADE7754 ON-CHIP REGISTERS All ADE7754 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register, then transferring the register data. For a full description of the serial interface protocol, see ...
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ADE7754 Address [A5:A0] Name R/W* Length 00h Reserved 01h AENERGY R 24 02h RAENERGY R 24 03h LAENERGY R 24 04h VAENERGY R 24 05h RVAENERGY R 24 06h LVAENERGY R 24 07h PERIOD R 15 08h TEMP R 8 ...
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Address [A5:A0] Name R/W* Length 13h LINCYC R/W 16 14h SAGCYC R/W 8 15h SAGLVL R/W 8 16h VPEAK R/W 8 17h IPEAK R/W 8 18h GAIN R/W 8 19h AWG R/W 12 1Ah BWG R/W 12 1Bh CWG R/W ...
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ADE7754 Address [A5:A0] Name R/W* Length 31h CIrmsOS R/W 12 32h AVrmsOS R/W 12 33h BVrmsOS R/W 12 34h CVrmsOS R/W 12 35h AAPGAIN R/W 12 36h BAPGAIN R/W 12 37h CAPGAIN R/W 12 38h AVGAIN R/W 12 39h BVGAIN ...
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Operational Mode Register (0Ah) The general configuration of the ADE7754 is defined by writing to the OPMODE register. Table IX summarizes the functionality of each bit in the OPMODE register. Bit Bit Default Location Mnemonic Value Description 0 DISHPF 0 ...
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ADE7754 Gain Register (18h) The gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing to the gain register. Table X summarizes the functionality of each bit in the ...
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Measurement Mode Register (0Bh) The configuration of the period and peak measurements made by the ADE7754 are defined by writing to the MMODE register. Table XII summarizes the functionality of each bit in the MMODE register. Bit Bit Default Location ...
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ADE7754 Watt Mode Register (0Dh) The phases involved in the active energy measurement of the ADE7754 are defined by writing to the WATMODE register. Table XIV summarizes the functionality of each bit in the WATMODE register. Bit Bit Default Location ...
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Interrupt Enable Register (0Fh) When an interrupt event occurs in the ADE7754, the IRQ logic output goes active low if the enable bit for this event is Logic 1 in this register. The IRQ logic output is reset to its ...
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ADE7754 Interrupt Status Register (10h)/Reset Interrupt Status Register (11h) The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7754, the corresponding flag in the interrupt status register is ...
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COPLANARITY 0.10 REV. 0 OUTLINE DIMENSIONS 24-Lead Standard Small Outline Package [SOIC] Wide Body (RW-24) Dimensions shown in millimeters and (inches) 15.60 (0.6142) 15.20 (0.5984 7.60 (0.2992) 7.40 (0.2913) 10.65 (0.4193 10.00 ...
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