ISL33001IRTZ-T Intersil, ISL33001IRTZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL33001IRTZ-T
• Description: IC BUS BUFF HOTSWAP 2WR 8TDFN
• Manufacturer: Intersil
• Type: I²C-Bus and SMBus Switchr

Specifications of ISL33001IRTZ-T

• Applications: General Purpose, Buffer/Bus Extender
• Internal Switch(s): Yes
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-WDFN Exposed Pad
• For Use With: ISL33001MSOPEVAL1Z - EVAL BOARD ISL33001 8MSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application Information
The ISL33001, ISL33002, ISL33003 ICs are 2-Wire
Bidirectional Bus Buffers designed to drive heavy
capacitive loads in open-drain/open-collector systems.
The ISL33001, ISL33002, ISL33003 incorporate rise time
accelerator circuitry that improves the rise time for
systems that use a passive pull-up resistor for logic
HIGH. These devices also feature hot swapping circuitry
for applications that require hot insertion of boards into a
host system (i.e., servers racks and I/O card modules).
The ISL33001 features a logic output flag (READY) that
signals the status of the buffer and an EN pin to enable or
disable the buffer. The ISL33002 features two separate
supply pins for voltage level shifting on the I/O pins and
a logic input to disable the rise time accelerator circuitry.
The ISL33003 features an EN pin and the level shifting
functionality.
I
The ISL33001, ISL33002, ISL33003 ICs are I
SMBUS compatible devices, designed to work in
open-drain/open-collector bus environments. The ICs
support both clock stretching and bus arbitration on the
SDA and SCL pins. They are designed to operate from DC
to more than 400kHz, supporting Fast Mode data rates of
the I
In addition, the buffer rise time accelerators are designed
to increase the capacitive drive capability of the bus.
2
C and SMBUS Compatibility
2
C specification.
SDA_IN
ISL33001 and ISL33003
SCL_IN
V
CC1
EN
M1
M3
9
ISL33001, ISL33002, ISL33003
FIGURE 8. CIRCUIT BLOCK DIAGRAM
2
START-UP CIRCUITRY
C and
LOGIC CONTROL
ACCELERATOR
PRECHARGE
RISE TIME
CIRCUIT
U1
U3
U2
U4
With careful choosing of components, driving a bus with
the I
400kHz data rate is possible.
Start-Up Sequencing and Hot Swap Circuitry
The ISL33001, ISL33002, ISL33003 buffers contain
undervoltage lock out (UVLO) circuitry that prevents
operation of the buffer until the IC receives the proper
supply voltage. For V
approximately 1.8V on the rising edge of the supply
voltage. Externally driven signals at the SDA/SCL pins
are ignored until the device supply voltage is above 1.8V.
This prevents communication errors on the bus until the
device is properly powered up. The UVLO circuitry is also
triggered on the falling edge when the supply voltage
drops below 1.7V.
Once the IC comes out of the UVLO state, the buffer will
remain disconnected until it detects a valid connection
state. A valid connection state is either a BUS IDLE
condition (see Figure 2) or a STOP BIT condition (a rising
edge on SDA_IN when SCL_IN is high) along with the
SCL_OUT and SDA_OUT pins being logic high.
Note - For the ISL33001 and ISL33003 with EN pins,
after coming out of UVLO, there will be an additional
delay from the enable circuitry if the EN pin voltage is not
rising at the same time as the supply pins (see Figure 1)
before a valid connection state can be established.
2
C specified maximum bus capacitance of 400pF at
CC1
and V
M5
V
ACC
ISL33002 and ISL33003
ISL33002 only
CC2
M2
M4
CC2
READY
ISL33001 only
, this voltage is
SDA_OUT
SCL_OUT
September 30, 2010
FN7560.2