LTC1155CS8 Linear Technology, LTC1155CS8 Datasheet - Page 6

• Manufacturer Part Number: LTC1155CS8
• Description: IC MOSFET DVR HI-SIDE DUAL 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1155CS8

• Configuration: High-Side
• Input Type: Non-Inverting
• Delay Time: 450µs
• Number Of Configurations: 2
• Number Of Outputs: 2
• Voltage - Supply: 4.5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -

LTC1155
OPERATIO
Gate Charge Pump
Gate drive for the power MOSFET is produced by an
adaptive charge pump circuit that generates a gate voltage
substantially higher than the power supply voltage. The
charge pump capacitors are included on-chip and, there-
fore, no external components are required to generate the
gate drive.
Drain Current Sense
The LTC1155 is configured to sense the drain current of
the power MOSFET in high side applications. An internal
100mV reference is compared to the drop across a sense
resistor (typically 0.002 to 0.1 ) in series with the drain
A
Protecting the MOSFET
The MOSFET is protected against destruction by removing
drive from the gate as soon as an overcurrent condition is
detected. Resistive and inductive loads can be protected
with no external time delay. Large capacitive or lamp
loads, however, require that the overcurrent shutdown
function be delayed long enough to start the load but short
enough to ensure the safety of the MOSFET.
Example Calculations
Consider the circuit of Figure 1. A power MOSFET is driven
by one side of an LTC1155 to switch a high inrush current
load. The drain sense resistor is selected to limit the
maximum DC current to 3.3A.
A time delay is introduced between R
sense pin of the LTC1155 which provides sufficient delay
to start a high inrush load such as large supply capacitors.
In this example circuit, we have selected the IRLZ34
because of its low R
6
PPLICATI
R
SEN
= V
= 0.1/3.3A
= 0.03
SEN
O
/I
U
TRIP
DS(ON )
U
S
I FOR ATIO
(0.05 with V
U
W
SEN
GS
= 5V). The FET
and the drain
U
lead. If the drop across this resistor exceeds the internal
100mV threshold, the input latch is reset and the gate is
quickly discharged by a large N-channel transistor.
Controlled Gate Rise and Fall Times
When the input is switched ON and OFF, the gate is
charged by the internal charge pump and discharged in a
controlled manner. The charge and discharge rates have
been set to minimize RFI and EMI emissions in normal
operation. If a short circuit or current overload condition
is encountered, the gate is discharged very quickly (typi-
cally a few microseconds) by a large N-channel transistor.
drops 0.1V at 2A and, therefore, dissipates 200mW in
normal operation (no heat sinking required).
If the output is shorted to ground, the current through the
FET rises rapidly and is limited by the R
the drain sense resistor and the series resistance be-
tween the power supply and the FET. Series resistance in
the power supply can be substantial and attributed to
many sources including harness wiring, PCB traces,
supply capacitor ESR, transformer resistance or battery
resistance.
IN1
Figure 1. Adding an RC Delay
LTC1155
GND
V
S
GND
V
S
= 5.0V
DS1
G1
C
0.22 F
DLY
R
270k
DLY
DS(ON)
LOAD
1155 F01
of the FET,
IRLZ34
R
0.03
SEN