VND830SP13TR STMicroelectronics, VND830SP13TR Datasheet - Page 11

IC DRIVER 2CH HI-SIDE POWERSO-10

VND830SP13TR

Manufacturer Part Number
VND830SP13TR
Description
IC DRIVER 2CH HI-SIDE POWERSO-10
Manufacturer
STMicroelectronics
Type
High Sider
Datasheet

Specifications of VND830SP13TR

Input Type
Non-Inverting
Number Of Outputs
2
On-state Resistance
60 mOhm
Current - Peak Output
9A
Voltage - Supply
5.5 V ~ 36 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
PowerSO-10 Exposed Bottom Pad
Supply Voltage (min)
5.5 V
Supply Current
40 mA
Maximum Power Dissipation
73500 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Switch Type
High Side
Power Switch On Resistance
60mOhm
Output Current
9A
Package Type
PowerSO
Operating Temperature (min)
-40C
Operating Temperature (max)
150C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
10
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output / Channel
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-3306-2

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VND830SP
Table 12.
Table 13.
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
Test pulse
Output voltage > V
proper operation without replacing the device.
Output current < I
ISO T/R
7637/1
Normal operation
Current limitation
Overtemperature
3a
3b
Undervoltage
1
2
4
5
Overvoltage
Conditions
Truth table
Electrical transient requirements
+ 26.5V
+ 25V
+ 25V
- 25V
- 25V
- 4V
OL
OL
I
(1)
(1)
(1)
(1)
(1)
(1)
+ 46.5V
+ 50V
+ 50V
- 50V
- 50V
- 5V
Doc ID 7380 Rev 4
II
Input
(1)
H
H
H
H
H
H
H
H
(1)
(1)
L
L
L
L
L
L
L
(1)
(1)
(2)
+ 66.5V
- 100V
+ 75V
+ 75V
- 75V
- 6V
III
(1)
(1)
(1)
(1)
(1)
Test level
(2)
Output
+ 86.5V
+ 100V
+ 100V
- 100V
- 150V
- 7V
H
X
X
H
H
H
L
L
L
L
L
L
L
L
L
IV
(1)
(1)
(1)
(1)
(1)
(2)
Electrical specifications
Delays and impedance
100ms, 0.01
0.2ms, 10
0.1µs, 50
0.1µs, 50
400ms, 2
2ms, 10
(T
(T
j
j
Status
< T
> T
H
H
H
H
X
X
H
H
H
H
L
L
L
TSD
TSD
) H
) L
11/27

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