VND830LSP13TR STMicroelectronics, VND830LSP13TR Datasheet - Page 11

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VND830LSP13TR

Manufacturer Part Number
VND830LSP13TR
Description
IC DRVR HISIDE 2CH POWERSO10
Manufacturer
STMicroelectronics
Type
High Sider
Datasheet

Specifications of VND830LSP13TR

Input Type
Non-Inverting
Number Of Outputs
2
On-state Resistance
60 mOhm
Current - Peak Output
23A
Voltage - Supply
5.5 V ~ 36 V
Operating Temperature
-40°C ~ 150°C
Mounting Type
Surface Mount
Package / Case
PowerSO-10 Exposed Bottom Pad
Switch Type
High Side
Power Switch Family
VND830LSP
Power Switch On Resistance
60mOhm
Output Current
23A
Mounting
Surface Mount
Supply Current
12uA
Package Type
PowerSO
Operating Temperature (min)
-40C
Operating Temperature (max)
150C
Operating Temperature Classification
Automotive
Pin Count
10
Power Dissipation
74W
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output / Channel
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
VND830LSP13TR
Manufacturer:
ST
0
Part Number:
VND830LSP13TR
Manufacturer:
ST
Quantity:
20 000
VND830LSP
Table 12.
Table 13.
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
Test pulse
Output voltage > V
proper operation without replacing the device.
Output current < I
ISO T/R
7637/1
Normal operation
Current limitation
Overtemperature
3a
3b
Undervoltage
1
2
4
5
Overvoltage
Conditions
Truth table
Electrical transient requirements
+ 26.5V
+ 25V
+ 25V
- 25V
- 25V
- 4V
OL
OL
I
(1)
(1)
(1)
(1)
(1)
(1)
+ 46.5V
+ 50V
+ 50V
- 50V
- 50V
- 5V
Doc ID 9431 Rev 4
II
Input
(1)
H
H
H
H
H
H
H
H
(1)
(1)
L
L
L
L
L
L
L
(1)
(1)
(2)
+ 66.5V
- 100V
+ 75V
+ 75V
- 75V
- 6V
III
(1)
(1)
(1)
(1)
(1)
Test level
(2)
Output
+ 86.5V
+ 100V
+ 100V
- 100V
- 150V
- 7V
H
X
X
H
H
H
L
L
L
L
L
L
L
L
L
IV
(1)
(1)
(1)
(1)
(1)
(2)
Electrical specifications
Delays and impedance
100ms, 0.01
0.2ms, 10
0.1µs, 50
0.1µs, 50
400ms, 2
2ms, 10
(T
(T
j
j
Status
< T
> T
H
H
H
H
X
X
H
H
H
H
L
L
L
TSD
TSD
) H
) L
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