MC33932VW Freescale Semiconductor, MC33932VW Datasheet - Page 8
MC33932VW
Manufacturer Part Number
MC33932VW
Description
IC H-BRIDGE THROTTLE CTRL 44HSOP
Manufacturer
Freescale Semiconductor
Type
H Bridger
Datasheet
1.MC33932VW.pdf
(21 pages)
Specifications of MC33932VW
Input Type
Non-Inverting
Number Of Outputs
2
On-state Resistance
120 mOhm
Current - Output / Channel
5A
Current - Peak Output
11A
Voltage - Supply
8 V ~ 28 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
44-HSOP
Product
H-Bridge Drivers
Rise Time
3 us
Fall Time
3 us
Supply Voltage (max)
28 V
Supply Voltage (min)
- 0.3 V
Supply Current
80 uA
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Bridge Type
H-Bridge
Maximum Turn-on Delay Time
1 ms
Minimum Operating Temperature
- 40 C
Number Of Drivers
4
Output Current
5 A
Output Voltage
7 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC33932VW
Manufacturer:
FRESSCAL
Quantity:
20 000
Table 4. Dynamic Electrical Characteristics
values noted reflect the approximate parameter means at T
8
TIMING CHARACTERISTICS
Notes
33932
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
PWM Frequency
Maximum Switching Frequency During Current Limit Regulation
Output ON Delay
Output OFF Delay
I
I
Disable Delay Time
Output Rise and Fall Time
Short-circuit / Over-temperature Turn-OFF (Latch-OFF) Time
Power-ON Delay Time
Output MOSFET Body Diode Reverse Recovery Time
Charge Pump Operating Frequency
20.
21.
22.
23.
24.
25.
26.
27.
28.
LIM
LIM
Characteristics noted under conditions 8.0 V ≤ V
V
V
Output Constant-OFF Time
Blanking Time
PWR
PWR
The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to
fully enhance the high side MOSFETs.
The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
* Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
output response signal. See
The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
The time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators may have time
to act.
* Disable Delay Time measurement is defined in
Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V
= 3.0 ohm. See
Load currents ramping up to the current regulation threshold become limited at the I
possess a di/dt that ramps up to the I
causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see
may cause junction temperatures to rise. Junction temperatures above ~160
or decrease, until ~175
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see
Parameter is Guaranteed By Design.
= 14 V
= 14 V
(20)
(22)
(22)
(24)
(25)
Figure
(28)
(26)
°
6, page 9.
C is reached, after which the T
Characteristic
(23)
Figure
(28)
DYNAMIC ELECTRICAL CHARACTERISTICS
4, page 9.
SCH
or I
SCL
(28)
threshold during the I
Figure
PWR
(27),
LIM
≤ 28 V, - 40°C ≤ T
5, page 9.
thermal latch-OFF will occur. Permissible operation within this fold back region
(21)
(28)
A
= 25°C under nominal conditions, unless otherwise noted.
LIM
blanking time, registering as a short-circuit event detection and
A
t
D
Symbol
°
≤ 125°C, GND = 0 V, unless otherwise noted. Typical
t
t
DISABLE
f
t
f
t
FAULT
t
C will cause the output current limit threshold to “fold back”,
D
PWM
F
t
MAX
D
POD
f
t
t
R R
CP
OFF
, t
ON
A
B
R
LIM
Figure
value (see
Min
1.5
15
12
75
–
–
–
–
–
–
–
–
Figure
Analog Integrated Circuit Device Data
9).
Figure
8). Operation in Current Limit mode
20.5
16.5
Typ
100
3.0
1.0
7.0
–
–
–
–
–
–
7). The short-circuit currents
Freescale Semiconductor
Max
150
PWR
8.0
8.0
8.0
5.0
11
20
18
12
32
27
–
= 14 V, R
Unit
MHz
kHz
kHz
ms
μs
μs
μs
μs
μs
μs
μs
ns
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