AMIS30624C6245RG ON Semiconductor, AMIS30624C6245RG Datasheet - Page 40

• Manufacturer Part Number: AMIS30624C6245RG
• Description: IC STEPPER DVR I2C 800MA 32-NQFP
• Manufacturer: ON Semiconductor
• Type: I2C Micro Stepping Motor Driverr

Specifications of AMIS30624C6245RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 8 V ~ 29 V
• Operating Temperature: -40°C ~ 165°C
• Mounting Type: Surface Mount
• Package / Case: 32-VSQFP
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 8 V to 29 V
• Supply Current: 800 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 766-1002-2

AMIS-30624
15.5 Transferring Data
15.5.1. Byte Format
Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer to AMIS-30624 is
restricted to eight. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first (See
Figure 27). If a slave can’t receive or transmit another complete byte of data, it can hold the clock line SCK LOW to force the master
into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCK.
15.5.2. Acknowledge
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulse is generated by the master. The transmitter
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge
clock pulse so that it remains stable LOW during the HIGH period of this clock pulse (see Figure 28). Of course, set-up and hold times
must also taken into account (see Table 6). When AMIS-30624 doesn’t acknowledge the slave address, the data line will be left HIGH.
The master can than generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer.
If AMIS-30624 as slave-receiver does acknowledge the slave address but later in the transfer cannot receive any more data bytes, this
is indicated by generating a not-acknowledge on the first byte to follow. The master generates than a STOP or a repeated START
condition.
If a master-receiver is involved in the transfer, it must signal the end of data to the slave-transmitter by not generating an acknowledge
on the last byte that was clocked out of the slave. AMIS-30624 as slave-transmitter shall release the data line to allow the master to
generate STOP or repeated START condition.
SCK
SDA
condition
START
START
MSB
1
SDA by master
SDA by slave
transmitter
receiver
SCK from
master
2
condition
START
START
Rev. 4 | Page 40 of 56 | www.onsemi.com
7
Figure 27: Data Transfer on the I
Figure 28: Acknowledge on the I
clock puse from master
MSB
Aknowledge related
1
Acknowledgement
signal from slave
Master releases the Data line
8
2
Not acknowledged
Acknowledged
9
clock puse from master
Aknowledge related
Clock line held
low by slave
2
2
8
C-bus
C-bus
1
9
2
low if Acknowledged
Slave pulls data line
PC20070217.4
PC20070217.5
3-8
ACK
9
condition
STOP
STOP