AMIS30624C6245RG ON Semiconductor, AMIS30624C6245RG Datasheet - Page 42

• Manufacturer Part Number: AMIS30624C6245RG
• Description: IC STEPPER DVR I2C 800MA 32-NQFP
• Manufacturer: ON Semiconductor
• Type: I2C Micro Stepping Motor Driverr

Specifications of AMIS30624C6245RG

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: 800mA
• Voltage - Supply: 8 V ~ 29 V
• Operating Temperature: -40°C ~ 165°C
• Mounting Type: Surface Mount
• Package / Case: 32-VSQFP
• Product: Stepper Motor Controllers / Drivers
• Operating Supply Voltage: 8 V to 29 V
• Supply Current: 800 mA
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Load: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 766-1002-2

AMIS-30624
15.6.1.2 Reading Data to AMIS-30624
When reading data from AMIS-30624 two transmissions are needed:
1) The first transmission consists of two bytes of data:
2) The second transmission consists of the slave address and the read bit. Then the master can read the data bits on the SDA line on
every rising edge of signal SCK. After each byte of data the master has to acknowledge correct data reception by pulling SDA LOW.
The last byte is not acknowledged by the master and therefore the slave knows the end of transmission.
Notes:
15.7 7-bit Addressing
The addressing procedure for the I
selected by the master. The exception is the general call address which can call all devices. When this address is used all devices
should respond with an acknowledge. The second byte of the general call address then defines the action to be taken.
15.7.1. Definition of Bits in the First Byte
The first seven bits of the first byte make up the slave address. The eighth bit is the least significant bit (LSB). It determines the
direction of the message. If the LSB is a “zero” it means that the master will write information to a selected slave. A “one” in this position
means that the master will read information from the slave. When an address is sent, each device in a system compares the first seven
bits after the START condition with its address. If they match, the device considers itself addressed by the master as a slave-receiver or
slave-transmitter, depending on the R/ W bit.
(1)
(2)
(3)
• The first byte contains the slave address and the write bit.
• The second byte contains the address of an internal register in the AMIS-30624. This internal register address is stored in the
circuit RAM.
Each byte is followed by an acknowledgment bit as indicated by the A or Ā in the sequence.
I
START conditions are not positioned according to the proper format.
A START condition immediately followed by a STOP condition (void message
2
C-bus compatible devices must reset their bus logic on receipt of a START condition such that they all anticipate the sending of a slave address, even if these
S
Master to AMIS-30624
AMIS-30624 to Master
Slave Address
Figure 32: Master Reading Data from AMIS-30624: Second Transmission is Reading Data
Figure 31: Master Reading Data from AMIS-30624: First Transmission is Addressing
S
2
C-bus is such that the first byte after the START condition usually determines which slave will be
MSB
Slave Address
"0" = WRITE
R/W
Figure 33: First Byte after START Procedure
SLAVE ADDRESS
Rev. 4 | Page 42 of 56 | www.onsemi.com
A
"0" = WRITE
R/W
S = Start condition
P = Stop condition
A = Acknowledge (SDA = LOW)
A = No Acknowledge (SDA = HIGH)
A
Data
)
Internal Address
is an illegal format.
N bytes + Acknowledge
R/W
LSB
A
PC20070219.2
PC20070219.5
A
Data
P
PC20070219.3
A
P