ISL6443AIRZ-TK Intersil, ISL6443AIRZ-TK Datasheet - Page 14
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ISL6443AIRZ-TK
Manufacturer Part Number
ISL6443AIRZ-TK
Description
IC CTRLR SGL/STP DWN PWM 28-QFN
Manufacturer
Intersil
Datasheet
1.ISL6443AIRZ.pdf
(19 pages)
Specifications of ISL6443AIRZ-TK
Applications
Power Supplies
Current - Supply
2mA
Voltage - Supply
5.6 V ~ 24 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The zero frequency, the amplifier high-frequency gain, and
the modulator gain are chosen to satisfy most typical
applications. The crossover frequency will appear at the
point where the modulator attenuation equals the amplifier
high frequency gain. The only task that the system designer
has to complete is to specify the output filter capacitors to
position the load main pole somewhere within one decade
lower than the amplifier zero frequency. With this type of
compensation plenty of phase margin is easily achieved due
to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole
is positioned too much to the left side on the frequency axis
due to excessive output filter capacitance. In this case, the
ESR zero placed within the 1.2kHz to 30kHz range gives
some additional phase ‘boost’. Some phase boost can also
be achieved by connecting capacitor C
upper resistor R
value. Please refer to “Output Inductor Selection” and
“Output Capacitor Selection” on page 16 for further details.
Linear Regulator
The linear regulator controller is a transconductance
amplifier with a nominal gain of 2A/V. The N-Channel
MOSFET output device can sink a minimum of 50mA. The
reference voltage is 0.8V. With 0V differential at it’s input, the
controller sinks 21mA of current. An external PNP transistor
or PFET pass element can be used. The dominant pole for
the loop can be placed at the base of the PNP (or gate of the
PFET), as a capacitor from emitter to base (source to gate of
a PFET). Better load transient response is achieved,
however, if the dominant pole is placed at the output, with a
capacitor to ground at the output of the regulator.
Under no-load conditions, leakage currents from the pass
transistors supply the output capacitors, even when the
transistor is off. Generally this is not a problem since the
feedback resistor drains the excess charge. However,
charge may build up on the output capacitor making V
MODULATOR
G
M
= 17.5dB
FIGURE 17. FEEDBACK LOOP COMPENSATION
EA
F
CONVERTER
PO
1
of the divider that sets the output voltage
F
14
Z
R1
F
C
G
EA
TYPE 2 EA
Z
in parallel with the
= 18dB
R2
C2
C1
F
P
LDO
ISL6443A
rise above its set point. Care must be taken to ensure that
the feedback resistor’s current exceeds the pass transistors
leakage current over the entire temperature range.
The linear regulator output can be supplied by the output of
one of the PWMs. When using a PFET, the output of the
linear regulator will track the PWM supply after the PWM
output rises to a voltage greater than the threshold of the
PFET pass device. The voltage differential between the
PWM and the linear output will be the load current times the
r
waveform and the PWM (3.3V) start-up waveform.
Base-Drive Noise Reduction
The high-impedance base driver is susceptible to system
noise, especially when the linear regulator is lightly loaded.
Capacitively coupled switching noise or inductively coupled
EMI onto the base drive causes fluctuations in the base
current, which appear as noise on the linear regulator’s
output. Keep the base drive traces away from the step-down
converter, and as short as possible, to minimize noise
coupling. A resistor in series with the gate drivers reduces
the switching noise generated by PWM. Additionally, a
DS(ON)
FIGURE 18. LINEAR REGULATOR START-UP WAVEFORM
. Figure 18 shows the linear regulator (2.5V) start-up
60
50
40
30
20
10
FIGURE 19. LINEAR CONTROLLER GAIN
0
0.79
0.80
FEEDBACK VOLTAGE (V)
0.81
0.82
0.83
V
V
0.84
OUT2
OUT3
June 2, 2008
1V/DIV
1V/DIV
0.85
FN6600.2