ISL97651ARTZ-TK Intersil, ISL97651ARTZ-TK Datasheet - Page 8

• Manufacturer Part Number: ISL97651ARTZ-TK
• Description: IC LCD SUPPLY HP 4CHN 36-TQFN
• Manufacturer: Intersil

Specifications of ISL97651ARTZ-TK

• Applications: LCD TV/Monitor
• Current - Supply: 400µA
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 36-TQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
(Exposed Die Plate)
PIN NUMBER
10, 18, 28, 36
25, 26
12
13
14
15
16
17
19
20
21
22
23
24
27
29
30
31
32
33
34
35
11
1
2
3
4
5
6
7
8
9
PIN NAME
PGND2, 1
PGND3
NOUT
AGND
VSUP
POUT
VREF
CDEL
DELB
VIN1
COM
VINL
VIN2
CM2
DRN
CM1
FBP
FBN
ENL
FBB
LX1
LX2
LXL
FBL
CTL
C1+
C2+
C1-
C2-
N/A
CB
NC
EN
8
Input voltage, connect to pin 33 (V
Internal boost switch connection
Internal boost switch connection
Logic buck, boost strap pin
Buck converter output
Positive supply for charge pumps
Logic buck feedback pin
Buck compensation network pin
Input control for V
No connect. Connect to die pad and GND for improved thermal efficiency.
Lower reference voltage for V
V
is connected to DRN through a 30Ω resistor.
Positive charge pump out
Charge pump capacitor 1, negative connection
Charge pump capacitor 1, positive connection
Charge pump capacitor 2, negative connection
Charge pump capacitor 2, positive connection
Positive charge pump feedback pin
Reference voltage
Negative charge pump feedback pin
Power ground for V
Negative charge pump output
Logic buck supply voltage
Boost power grounds
Signal ground pin
Delay capacitor for start up sequencing, soft-start and fault detection timers.
Buck enable for V
Open drain NFET output to drive optional A
Boost compensation network pin
Input voltage, connect to pin 1 (V
Boost feedback pin
Enable for Boost, charge pumps and V
Connect exposed die plate on rear of package to ACGND and the PGND1, 2 pins. See “Layout
Recommendation” on page 18 for PCB layout thermal considerations.
ON
slice output: when CTL = 1, COM is connected to SRC through a 5Ω resistor; when CTL = 0, COM
ON
LOGIC
OFF
slice output
ISL97651
, V
output
ON
ON
and V
IN1
slice output
IN2
ON
)
)
ON
slice
slice (independent of ENL).
DESCRIPTION
VDD
delay PFET
April 24, 2009
FN7493.3