ISL6125IRZA Intersil, ISL6125IRZA Datasheet - Page 7

• Manufacturer Part Number: ISL6125IRZA
• Description: IC POWER SUPPLY SEQUENCER 24QFN
• Manufacturer: Intersil

Specifications of ISL6125IRZA

• Applications: Power Supply Sequencer
• Voltage - Supply: 1.5 V ~ 5.5 V
• Current - Supply: 200µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

Electrical Specifications
Descriptions and Operation
The ISL612X sequencer family consists of several four
channel voltage sequencing controllers in various
functional and personality configurations. All are designed
for use in multiple-voltage systems requiring power
sequencing of various supply voltages. Individual voltage
rails are gated on and off by external N-Channel MOSFETs,
the gates of which are driven by an internal charge pump to
V
With the four-channel ISL6123 the ENABLE must be
asserted high and all four voltages to be sequenced must
be above their respective user programmed Undervoltage
Lock Out (UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
capacitor values on the DLY_ON and DLY_OFF pins. Once
all four UVLO inputs and ENABLE are satisfied for 10ms,
RESET Output Low
RESET Output Capacitance
SYSRST Pull-Up Voltage
SYSRST Pull-Down Current
SYSRST Low Output Voltage
SYSRST Output Capacitance
SYSRST Low to GATE Turn-Off
GATE
GATE Turn-On Current
GATE Turn-Off Current
GATE Current Range
GATE Turn-On/Off Current Temperature
Coefficient
GATE Pull-Down High Current
GATE High Voltage
GATE Low Voltage
BIAS
IC Supply Current
ISL6123, ISL6130 Stand By IC Supply
Current
V
DD
DD
+ 5.3V (VQP) in a user programmed sequence.
Power-on Reset
PARAMETER
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
7
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
V
DD
= 1.5V to +5V, T
I
C
GATE_range
I
V
t
TC_I
I
I
SYMBOL
Cout_srst
I
GATEoff_h
Vpu_srst
delSYS_G
VDD_3.3V
VDD_1.5V
GATEoff_l
I
Vol_srst
I
V
V
I
OUT_RST
Ipu_1.5
V
DD
GATEon
VDD_5V
VDD_sb
V
Ipu_5
GATEh
GATEh
GATEl
RSTl
_POR
GATE
A
= T
J
Measured at V
pull-up resistors
V
V
V
GATE = 80% of V
GATE = 0V
GATE = V
Within IC I
GATE = V
V
V
Gate Low Voltage, V
V
V
V
V
= -40°C to +85°C, unless otherwise specified. Parameters with MIN and/or MAX
DD
DD
DD
DD
DD
DD
DD
DD
DD
= 1.5V
= 5V
= 1.5V, I
< 2V, T
> 2V
= 5V
= 3.3V
= 1.5V
= 5V, ENABLE = 0V
TEST CONDITIONS
DD
DD
GATE
J
, Disabled
, UVLO = 0V
OUT
= +25°C
the four DLY_ON capacitors are simultaneously charged
with 1µA current sources to the DLY_Vth level of 1.27V. As
each DLY_ON pin reaches the DLY_Vth level its associated
GATE will then turn-on with a 1µA source current to the
VQP voltage of V
sequentially turn-on. Once at DLY_Vth the DLY_ON pins
will discharge to be ready when next needed. After the
entire turn on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability after which the
RESET output will be released to go high. Subsequent to
turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~30µs) this is considered a
fault. RESET and SYSRST are pulled low and all GATEs
are simultaneously also pulled low. In this mode the GATEs
are pulled low with 88mA. Normal shutdown mode is
entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET is
DD
max-min
DD
= 5V with 5k
= 100µA
DD
+ 5V
= 1V
DD
V
DD
+ 5.3V. Thus, all four GATEs will
MIN
-1.4
0.8
+ 5V
V
V
DD
DD
-1.05
TYP
V
0.20
0.14
0.10
100
150
1.1
0.2
10
10
40
88
DD
+ 4.9V
+ 5.3V
5
0
MAX
0.35
-0.8
0.1
1.4
0.1
0.5
1
1
October 15, 2008
FN9005.10
nA/°C
UNIT
mV
mA
mA
mA
mA
pF
µA
µA
pF
µA
µA
µA
µA
ns
V
V
V
V
V
V