LM96194CISQ/NOPB National Semiconductor, LM96194CISQ/NOPB Datasheet - Page 21

• Manufacturer Part Number: LM96194CISQ/NOPB
• Description: IC TRUTHERM HDWR MONITOR 48-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®, TruTherm®r

Specifications of LM96194CISQ/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96194CISQTR

Special Notes
1.
2.
3.
4.
14.5.3.4 I
In this transaction the master sends a block of data to the LM96194 as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Special Notes:
1.
2.
1
S
Any attempts to write to bytes beyond normal address space are acknowledged by the LM96194 but are ignored.
Block writes do not wrap from address FFh back to 00h the address remains at FFh.
The Byte Count field is ignored by the LM96194. The master device may send more or less bytes and the LM96194 accepts
them.
The SMBus specification requires that block writes never exceed 32 data bytes. Meeting this requirement means that only 31
actual data bytes can be sent (the register address counts as one byte). The LM96194 does not care if this requirement is
met.
The master device asserts a START condition.
The master sends the 7-bit slave address followed by the write bit (low).
The addressed slave device asserts ACK.
The master sends the starting address of the block write.
The slave asserts ACK after each data byte.
The master sends data byte 1.
The slave asserts ACK.
The master continues to send data bytes and the slave asserts ACK for each byte.
The master asserts a STOP condition to end the transaction
Any attempts to write to bytes beyond normal address space are acknowledged by the LM96194 but are ignored.
Block writes do not wrap from address FFh back to 00h the address remains at FFh.
2
Slave
Address
2
C ™ Block Write
W
1
S
3
A
2
Slave
Address
4
Comman
d
F0h
(Block
Write)
W
5
A
3
A
6
Byte
Count
(N)
4
Register
Address
7
A
5
A
21
8
Data
Byte 1
(Start
Address)
6
Data
Byte 1
9
A
7
A
10
Data
Byte 2
…
8
Data
Byte N
11
A
…
…
A
12
Data
Byte N
9
P
www.national.com
A
13
P