LM96080CIMT/NOPB National Semiconductor, LM96080CIMT/NOPB Datasheet - Page 13

• Manufacturer Part Number: LM96080CIMT/NOPB
• Description: IC HARDWARE MONITOR 24-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM96080CIMT/NOPB

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Counter, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: I²C™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM96080CIM

3.0 USING THE LM96080
3.1 Power On
When power is first applied, the LM96080 performs a “power
on reset” on several of its registers. The power on condition
of registers is shown in
values are not shown have power on conditions that are in-
determinate (this includes the value RAM and WATCHDOG
limits). In most applications, usually the first action after pow-
er-on would be to write WATCHDOG limits into the Value
RAM.
3.2 Resets
Configuration Register INITIALIZATION bit (address 00h, bit
7) accomplishes the same function as power on reset. The
Value RAM conversion results (addresses 20h - 29h) and
Value RAM WATCHDOG limits (addresses 2Ah - 3Dh) are
not reset and will be indeterminate immediately after power
on. If the Value RAM contains valid conversion results and/or
Value RAM WATCHDOG limits have been previously set,
they will not be affected by the Configuration Register INI-
TIALIZATION (except for addresses 3Eh and 3Fh). Power on
reset or Configuration Register INITIALIZATION bit clear or
initialize the following registers (the initialized values are
shown in
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Value RAM Registers (only addresses 3Eh and 3Fh)
Configuration Register INITIALIZATION is accomplished by
setting bit 7 of the Configuration Register (address 00h) high.
This bit automatically clears after being set.
The LM96080 can be reset to its “power on state” by taking
NTEST_IN/Reset_IN pin low for at least 50 ns.
3.3 Using the Configuration Register
The Configuration Register (address 00h) provides control for
the LM96080. At power on, the ADC is stopped and
INT_Clear (bit 3) is asserted, clearing the INT and
RST_OUT/OS hardwire outputs. The Configuration Register
starts and stops the LM96080, enables and disables INT out-
puts, clears and sets GPI (CI) and GPO I/O pins, initiates reset
pulse on RST_OUT/OS pin, and provides the reset function
described in Section 3.2.
Bit 0 of the Configuration Register, START, controls the mon-
itoring loop of the LM96080. Setting bit 0 low stops the
LM96080 monitoring loop and puts the LM96080 in shutdown
mode, reducing power consumption. Serial Bus communica-
tion is possible with any register in the LM96080 although
Configuration Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Fan Divisor/RST_OUT/OS Register
OS Configuration/Temperature Resolution Register
Conversion Rate Register
Voltage/Temperature Channel Disable Register
Table
1):
Table
1. Registers whose power on
13
activity on these lines will increase consumption current. Tak-
ing bit 0 high starts the monitoring loop, described in more
detail subsequently.
Bit 1 of the Configuration Register, INT Enable, enables the
INT Interrupt hardwire output when this bit is taken high.
Bit 2 of the Configuration Register, INT Polarity Select, de-
fines whether the INT pin is NMOS or PMOS open drain.
Bit 3, INT_Clear, clears the INT output when taken high. The
LM96080 monitoring function will stop until bit 3 is taken low.
The content of the Interrupt Status Registers (addresses 01h
- 02h) will not be affected.
Bit 4, RESET, when taken high, will initiate a 10 ms RESET
signal on the RST_OUT/OS output when OS Pin Enable (ad-
dress 05h, bit 6) = 0 and RST Enable (address 05h, bit 7) =
1.
When bit 5, Chassis Clear, is taken high, the GPI (Chassis
Intrusion) pin is driven low for 10 ms.
Bit 6 of the configuration register, GPO, sets or clears the
GPO output. This pin can be used in software power control
by activating an external power control MOSFET.
3.4 Starting Conversions
Start the monitoring function (Analog inputs, temperature,
and fan speeds) in the LM96080 by writing to the Configura-
tion Register and setting INT_Clear (bit 3) low and Start (bit
0) high. The LM96080 then performs a round-robin monitoring
of all analog inputs, temperature, and fan speed inputs. The
sequence of items being monitored corresponds to locations
in the Value RAM (except for the Temperature reading) as
follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Fan 2
3.5 Reading Conversion Results
The conversion results are available in the Value RAM (ad-
dresses 20h - 29h). Conversions can be read at any time and
will provide the result of the last conversion. If a conversion is
in progress while a communication is started, that conversion
will be completed, and the internal register(s) will not be up-
dated until the communication is complete.
A typical sequence of events upon power on of the LM96080
would consist of:
1.
2.
3.
Temperature
IN0
IN1
IN2
IN3
IN4
IN5
IN6
Fan 1
Set WATCHDOG Limits
Set Interrupt Masks
Start the LM96080 monitoring process
www.national.com