MAX8599ETE+ Maxim Integrated Products, MAX8599ETE+ Datasheet - Page 20

• Manufacturer Part Number: MAX8599ETE+
• Description: IC CNTRLR STP DWN LDO 16-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX8599ETE+

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 1.4MHz
• Duty Cycle: 99.5%
• Voltage - Supply: 4.5 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TQFN Exposed Pad
• Frequency-max: 1.4MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the output capacitor is comprised of paralleling n
number of the same capacitors, then:
Thus, the resulting f
gle capacitor.
The total closed-loop gain must be equal to unity at the
crossover frequency, where the crossover frequency is
less than or equal to 1/5 the switching frequency (f
So the loop-gain equation at the crossover frequency is:
where G
G
The loop compensation is affected by the choice of out-
put filter capacitor due to the position of its ESR-zero
frequency with respect to the desired closed-loop
crossover frequency. Ceramic capacitors are used for
higher switching frequencies and have low capaci-
tance and low ESR; therefore, the ESR-zero frequency
is higher than the closed-loop crossover frequency.
Electrolytic capacitors (e.g., tantalum, solid polymer,
and OS-CON) are needed for lower switching frequen-
cies and have high capacitance (and some have high-
er ESR); therefore, the ESR-zero frequency can be
lower than the closed-loop crossover frequency. Thus,
the compensation design procedures are separated
into two cases:
Case 1: Crossover frequency is less than the out-
put-capacitor ESR-zero (f
The modulator gain at f
Since the crossover frequency is lower than the output
capacitor ESR-zero frequency and higher than the LC
double-pole frequency, the error-amplifier gain must
have a +1 slope at f
of the LC double pole, the loop crosses over at the
desired -1 slope.
The error amplifier has a dominant pole at a very low
frequency (~0Hz), and two additional zeros and two
additional poles as indicated by the equations below
and illustrated in Figure 7:
Low-Dropout, Wide-Input-Voltage,
Step-Down Controllers
20
MOD(FC)
______________________________________________________________________________________
EA(FC)
G
is the power-modulator gain at f
f
MOD(FC)
Z2_EA
f
Z1_EA
G
R
is the error-amplifier gain at f
EA(FC)
= 1 / (2 π x (R1 + R3) x C1)
ESR
C
= G
C
Z_ESR
O
= 1 / (2 π x R4 x C2)
so that, together with the -2 slope
= R
C
f
= n x C
C
MOD(DC)
x G
is:
≤ f
and
ESR_EACH
C
is the same as that of a sin-
MOD(FC)
S
< f
/ 5
EACH
Z_ESR
x (f
P_LC
/ n
= 1
).
/ f
C
C
.
)
2
C
, and
S
):
Note that f
converter closed-loop crossover frequency, f
when the error-amplifier gain has +1 slope, between
f
meet the requirement below:
The gain of the error amplifier between f
f
This gain is set by the ratio of R4/R1 (Figure 6), where
R1 is calculated as illustrated in the Setting the Output
Voltage section. Thus:
where f
Due to the underdamped (Q > 1) nature of the output
LC double pole, the first error-amplifier zero frequency
must be set less than the LC double-pole frequency in
order to provide adequate phase boost. Set the error-
amplifier first zero, f
frequency. Hence:
Set the error amplifier f
The error-amplifier gain between f
set by the ratio of R4/RM and is equal to:
where RM = R1 x R3 / (R1 + R3). Then:
The value of R3 can then be calculated as:
Now we can calculate the value of C1 as:
and C3 as:
Z2_EA
Z2_EA
G EA(fZ1_EA - fZ2_EA) = G EA(FC) x f Z2_EA / f C = f Z2_EA / (f C x G MOD(FC) )
RM = R4 x f
f
P3_EA
If f
f
p
is:
f
and f
Z2_EA
p
3
Z ESR
2
C3 = C2 / ((2 π x C2 x R4 x f
_
G
EA
_
_
R4 = R1 x f
EA
EA(fZ1_EA - fZ2_EA)
Z2_EA
= 1 / (2 π x R4 x (C2 x C3 / (C2 + C3)))
P2_EA
= R4 x f
= f
at
f
C1 = 1 / (2 π x R3 x f
at
P2_EA
R3 = R1 x RM / (R1 – RM)
P_LC
C2 = 2 / (π x R4 x f
G
is greater than
P_LC
f
2
s
f
EA(FC)
2
s
and f
. The error-amplifier gain at f
and f
Z1_EA
if f
/ (G
C
.
= 1 / (2 π x R3 x C1)
Z2_EA
Z ESR
P2_EA
x G
_
P2_EA
= 1 / G
p
EA(fZ1_EA - fZ2_EA)
, at 1/4 of the LC double-pole
3
MOD(FC)
_
/ (f
EA
is less than
at f
x (f
C
are chosen to have the
MOD(FC)
f
2
at f
s
Z_ESR
x G
P2_EA
,
P_LC
Z ESR
p2_EA
P2_EA
/ f
then set
MOD(FC)
_
P3_EA
P2_EA
and
)
/ f
f
2
s
)
.
P_LC
.
and f
) - 1)
x f
)
Z1_EA
P2_EA
)
C
P3_EA
, occur
C
must
)
and
is