ISL8106CRZ Intersil, ISL8106CRZ Datasheet - Page 12

• Manufacturer Part Number: ISL8106CRZ
• Description: IC PWM CTRLR SGL PHASE 16-QFN
• Manufacturer: Intersil

Specifications of ISL8106CRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 600kHz
• Voltage - Supply: 7 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Frequency-max: 600kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Duty Cycle: -

paralleled to adjust the ESR to achieve the required V
The inductance of the capacitor can cause a brief voltage dip
when the load transient has an extremely high slew rate.
Low inductance capacitors constructed with reverse
package geometry are available.
A capacitor dissipates heat as a function of RMS current. Be
sure that I
capacitors so that they operate below the maximum rated
RMS current. Take into account that the specified value of a
capacitor can drop as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 5 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as:
Where:
I
IN_RMS
FIGURE 5. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
- I
- x is a multiplier (0 to 1) corresponding to the inductor
- D is the duty cycle that is adjusted to take into account
D
peak-to-peak ripple amplitude expressed as a
percentage of I
the efficiency of the converter which is written as:
0.55
0.45
0.35
0.25
0.15
0.05
MAX
0.6
0.5
0.4
0.3
0.2
0.1
=
0
0
------------------------- -
V
=
PP
is the maximum continuous I
IN
V
---------------------------------------------------------------------------------------------------- -
OUT
(
⋅
0.1
is shared by a sufficient quantity of paralleled
I
EFF
MAX
0.2
2
MAX
⋅
(
D D
0.3
–
(0% to 100%)
I
MAX
2
DUTY CYCLE
x = 1
x = 0.75
x = 0.50
x = 0.25
x = 0
0.4
)
12
)
+
⎛
⎝
0.5
x I
⋅
MAX
0.6
LOAD
2
⋅
----- -
12
0.7
D
⎞
⎠
of the converter
0.8
0.9
(EQ. 14)
PP
.
1
ISL8106
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
terminal of the top-side MOSFET and the source terminal of
the bottom-side MOSFET, in order to reduce the voltage
ringing created by the switching current across parasitic
circuit elements.
MOSFET Selection and Considerations
Typically, MOSFETS cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETS used in the power conversion stage of the
converter should have a maximum V
the upper voltage tolerance of the input power source, and
the voltage spike that occurs when the MOSFET switches
off. Placing a low ESR ceramic capacitor as close as
practical across the drain of the top-side MOSFET and the
source of the bottom-side MOSFET will reduce the
amplitude of the turn-off voltage spike.
The MOSFET input capacitance C
source resistance r
related; reduction of r
of C
converter in different ways. The r
loss when the MOSFET is completely turned on and
conducting current. The C
the MOSFET is actively switching. Switching time increases
as C
conduct current while the drain to source voltage is still
present. The power dissipation during this time is substantial
so it must be kept as short as practical. Often the top-side
MOSFET and the bottom-side MOSFET are different
devices due to the trade-offs that have to be made between
C
The bottom-side MOSFET power loss is dominated by
r
PWM switching cycle; the r
switching loss is small for the bottom-side MOSFET even
though C
because the drain to source voltage is clamped by the body
diode. The top-side MOSFET power loss is dominated by
C
PWM switching cycle; the C
switching loss of the top-side MOSFET is large compared to
the bottom-side MOSFET because the drain to source
voltage is not clamped. For the bottom-side MOSFET, its
power loss can be assumed to be the conduction loss only
and can be written as:
For the top-side MOSFET, its conduction loss can be written
as:
P
P
DS(ON)
ISS
ISS
CONBS
CONTS
ISS
ISS
and r
because it conducts current for the minority of the
. These two parameters affect the efficiency of the
increases. When the MOSFET switches it will briefly
⋅
because it conducts current for the majority of the
⋅
D V
D V
ISS
(
(
DS(ON)
IN
IN
is large due to the low r
)
)
≈
=
[
.
I
[
LOAD
DS(ON)
I
LOAD
DS(ON)
]
2
]
2
ISS
, are to an extent, inversely
•
DS(ON)
r
•
ISS
DS ON
r
DS ON
typically results in an increase
affects the power loss when
(
(
should be small. The
DS(ON)
)BS
ISS,
should be small. The
)TS
DS(ON)
DS
•
•
[
and on-state drain to
1 D V
D
rating that exceeds
affects the power
–
(
V
IN
of the device,
(
)
IN
November 10, 2006
)
]
(EQ. 15)
(EQ. 16)
FN9283.1