ISL6741IB Intersil, ISL6741IB Datasheet - Page 20

• Manufacturer Part Number: ISL6741IB
• Description: IC CTRLR PWM DBL-ENDED 16-SOIC
• Manufacturer: Intersil

Specifications of ISL6741IB

• Pwm Type: Current Mode
• Number Of Outputs: 2
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 9 V ~ 16 V
• Buck: No
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

method to achieve this. The divider between RTC and GND
formed by R13 and R15 determines the percent of maximum
duty cycle that corresponds to a short circuit. The divider
ratio formed by R13 and R15 is
Therefore, the duty cycle that corresponds to a short circuit
is 6.8% of D max (97.9%), or ~6.6%.
Performance
The major performance criteria for the converter are
efficiency, and to a lesser extent, load regulation. Efficiency,
load regulation and line regulation performance are
demonstrated in the following Figures.
As expected, the output voltage varies considerably with line
and load when compared to an equivalent converter with
closed loop feedback. However, for applications where tight
---------------------------- -
R13
R15
+
R15
FIGURE 11. LOAD REGULATION AT V
FIGURE 10. EFFICIENCY vs LOAD V
FIGURE 12. LINE REGULATION AT I
12.25
12.00
11.75
11.50
11.25
12.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
100
95
90
85
80
75
70
=
11
45
0
----------------------------------- -
1.27k
0
1.27k
46
1
1
+
17.4k
47
2
2
LOAD CURRENT (A)
INPUT VOLTAGE (V)
LOAD CURRENT (A)
48
3
3
=
20
0.068
49
4
4
50
5
5
51
6
6
OUT
IN
52
7
7
IN
= 48V
= 48V
= 1A
53
8
8
t
(EQ. 24)
54
ISL6740, 1SL6741
9
9
regulation is not required, such as those application that use
downstream DC/DC converters, this design approach is
viable.
Waveforms
Typical waveforms can be found in the following Figures.
Figure 13 shows the output voltage during start up.
Figure 14 shows the output voltage ripple and noise at a 5A
load.
Figures 15 and 16 show the voltage waveforms at the
switching node shared by the upper FET source and the lower
FET drain. In particular, Figure 16 shows near ZVS operation
at 8A of load when the upper FET is turning off and the lower
FET turning on. There is insufficient energy stored in the
leakage inductance to allow complete ZVS operation.
However, since the energy stored in the node capacitance is
proportional to V
recovered. Figure 17 shows the switching transition between
outputs, OUTA and OUTB during steady state operation. The
deadtime duration of 48.6ns is clearly shown.
FIGURE 14. OUTPUT RIPPLE AND NOISE (20MHz BW)
FIGURE 13. OUTPUT SOFT-START
2
, a significant portion of the energy is still
July 13, 2007
FN9111.4