ISL6336BIRZ Intersil, ISL6336BIRZ Datasheet - Page 12

• Manufacturer Part Number: ISL6336BIRZ
• Description: IC CTRLR PWM SYNC BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6336BIRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To understand the reduction of the ripple current amplitude in
the multiphase circuit, examine Equation 1, which represents
an individual channel’s peak-to-peak inductor current.
In Equation 1, V
voltages respectively, L is the single-channel inductor value,
and f
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the expression
for the peak-to-peak current after the summation of N
symmetrically phase-shifted inductor currents in Equation 2.
Peak-to-peak ripple current decreases by an amount
proportional to the number of channels. Output-voltage ripple is
a function of capacitance, capacitor equivalent series
resistance (ESR), and inductor ripple current. Reducing the
inductor ripple current allows the designer to use fewer or less
costly output capacitors.
I
PP
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT
=
S
(
--------------------------------------------------------- -
V
is the switching frequency.
IN
PWM1, 5V/DIV
–
L f
INPUT-CAPACITOR CURRENT 10A/DIV
V
⋅
IL1 + IL2 + IL3, 7A/DIV
FOR 3-PHASE CONVERTER
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
OUT
S
IN
⋅
CHANNEL 1
INPUT CURRENT
10A/DIV
V
IL1, 7A/DIV
) V
and V
IN
⋅
OUT
CHANNEL 2
INPUT CURRENT
10A/DIV
PWM3, 5V/DIV
OUT
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
12
1µs/DIV
are the input and the output
IL3, 7A/DIV
PWM2, 5V/DIV
IL2, 7A/DIV
(EQ. 1)
ISL6336B
Another benefit of interleaving is to reduce the input ripple
current. The input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve the overall system cost and size by lowering the
input ripple current and allowing the designer to reduce the
cost of input capacitance. The example in Figure 2 illustrates
the input currents from a three-phase converter combining to
reduce the total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
input capacitor current. The single-phase converter must use
an input capacitor bank with twice the RMS current capacity as
the equivalent 3-phase converter.
Figures 21, 22 and 23 in the section entitled “Input Capacitor
Selection” on page 29 can be used to determine the input
capacitor RMS current based on the load current, the duty
cycle, and the number of channels. They are provided as
aids in determining the optimal input capacitor solution.
Figure 24 shows the single phase input-capacitor RMS
current for comparison.
PWM Modulation Scheme
The ISL6336B adopts Intersil's proprietary Active Pulse
Positioning (APP) modulation scheme to improve the
transient performance. APP control is a unique dual-edge
PWM modulation scheme with both PWM leading and
trailing edges being independently moved to provide the
best response to the transient loads. The PWM frequency,
however, is constant and set by the external resistor
between the FS pin and GND.
To further improve the transient response, the ISL6336B also
implements Intersil's proprietary Adaptive Phase Alignment
(APA) technique. The APA, with sufficiently large load step
currents, can turn on all phases simultaneously.
With both APP and APA control, ISL6336B can achieve
excellent transient performance and reduce the demand on
the output capacitors.
Under steady state conditions the operation of the ISL6336B
PWM modulator appears to be that of a conventional trailing
edge modulator. Conventional analysis and design methods
can therefore be used for steady state and small signal
operation.
PWM and PSI# Operation
The timing of each converter is set by the number of active
channels. The default channel setting for the ISL6336B is
six. The switching cycle is defined as the time between PWM
pulse termination signals of each channel. The cycle time of
the pulse termination signal is the inverse of the switching
I
C P-P
(
)
=
(
------------------------------------------------------------------------ -
V
IN
–
(
N V
L f
⋅
⋅
S
OUT
⋅
V
IN
)
) V
⋅
OUT
August 31, 2010
(EQ. 2)
FN6696.2
RMS