ISL6336BIRZ Intersil, ISL6336BIRZ Datasheet - Page 18

• Manufacturer Part Number: ISL6336BIRZ
• Description: IC CTRLR PWM SYNC BUCK 48-QFN
• Manufacturer: Intersil

Specifications of ISL6336BIRZ

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a direction
which works to achieve the load-line regulation required by
these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
VID7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
TABLE 3. VR11 VID 8-BIT (Continued)
VID5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
VID3
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
18
VID2
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
VID1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
VID0 VOLTAGE
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0.61875
0.61250
0.60625
0.60000
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
OFF
ISL6336B
As shown in Figure 6, a current proportional to the average
current of all active channels, I
load-line regulation resistor R
across R
creating an output voltage droop with a steady-state value
defined in Equation 8.
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
Where V
programmed offset voltage, I
of the converter, R
the ISEN+ pin, and R
active channel number, and R
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
Output-Voltage Offset Programming
The ISL6336B allows the designer to accurately adjust the
offset voltage. When resistor, R
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I
R
regulated to 0.4V, and I
between DAC and REF, R
product (I
These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to set R
For Positive Offset (connect R
For Negative Offset (connect R
R
V
V
R
R
DROOP
OFS
LL
DROOP
OUT
OFS
OFS
=
is connected to ground, the voltage across it is
=
=
=
------------
R
N
. The output voltage as a function of load current is
REF
FB
V
FB
1.6 R
--------------------------- -
0.4 R
--------------------------- -
V
V
OFS
=
REF
OFFSET
OFFSET
⋅
I
is proportional to the output current, effectively
⋅
⋅
AVG
is the reference voltage, V
----------------- -
R
x R
–
REF
REF
ISEN
R
V
X
⋅
OFS
OFS
ISEN
R
FB
FB
) is equal to the desired offset voltage.
–
OFS
⎛
⎜
⎝
is the sense resistor connected to
I
------------ -
is the feedback resistor, N is the
OUT
N
REF
flows out of OFS. A resistor
OUT
FB
⋅
X
, is selected so that the
OFS
AVG
OFS
OFS
OFS
----------------- - R
R
is the DCR, or R
. The resulting voltage drop
ISEN
R
OFS
is the total output current
, flows from FB through a
X
to VCC):
, is connected between
) to flow into OFS. If
to GND):
:
⋅
OFS
FB
⎞
⎟
⎠
is the
SENSE
August 31, 2010
(EQ. 12)
(EQ. 11)
(EQ. 10)
(EQ. 8)
(EQ. 9)
FN6696.2