MAX17528GTJ+ Maxim Integrated Products, MAX17528GTJ+ Datasheet - Page 28

• Manufacturer Part Number: MAX17528GTJ+
• Description: IC PWM CTRLR STP-DWN 32TQFN-EP
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17528GTJ+

• Applications: Controller, Intel IMVP-6.5™ GMCH
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 5. IMVP-6.5 Sleep Transition
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The MAX17528 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an inter-
nal capacitor and current-source programmed by
R
tion time depends on R
and the accuracy of the slew-rate controller (C
accuracy). The slew rate is not dependent on the total
output capacitance, as long as the surge current is less
than the current limit. For all dynamic VID transitions,
the transition time (t
where dV
slew rate, V
V
Accuracy in the Electrical Characteristics table for
slew-rate limits. For soft-start and shutdown, the con-
troller automatically reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. Excluding the
load current, the average inductor current required to
make an output voltage transition is:
28
TIME
NEW
______________________________________________________________________________________
NOTE: DPRSLPVR = SKIP.
is the new target voltage. See TIME Slew-Rate
VID (D0–D6)
to transition the output voltage. The total transi-
ACTIVE VID
DPRSLPVR
CPU CORE
VOLTAGE
PWRGD
TARGET
CLKEN
DH
OLD
I
L
t
TRAN
≅
/dt = 12.5mV/µs x 71.5kΩ/R
is the original output voltage, and
C
TRAN
OUT
BLANK HIGH IMPEDANCE
=
(
) is given by:
×
BLANK LOW
TIME
dV
LFM VID
V
(
NEW
dV
TARGET
TARGET
, the voltage difference,
−
V
20µs typ
OLD
t
BLANK
/
dt
/
dt
)
)
TIME
POSSIBLE VID CHANGE
PULSE SKIPPING
is the
SLEW
where dV
is the total output capacitance.
The IMVP-6.5 CPU enters a low-power state to con-
serve power (Figure 5). The processor enters this state
by initially setting the core voltage to the LFM voltage
level (no LSB stepping). Upon reaching the LFM volt-
age level, the processor asserts DPRLPVR, which is
connected to SKIP as shown in Figure 1, signaling that
a very low current state has been entered. However,
the processor can still lower the core voltage by LSB
increments to further reduce power consumption under
this very low-power sleep state. The processor exits the
sleep state by pulling DPRSLVPR low and ramping up
the core voltage by LSB increments. During all VID
transitions, the MAX17528 blanks PWRGD (forced high
impedance) and CLKEN (forced low) until 20µs after
the internal target (which moves at the slew rate set by
R
TIME
) reaches the selected VID code.
IMVP-6.5 Low-Power Sleep Transition
TARGET
BLANK HIGH IMPEDANCE
/dt is the required slew rate and C
BLANK LOW
1-PHASE FORCED PWM
20µs typ
t
BLANK
HFM VID
HFM VID
LFM VID
OUT