MAX17528GTJ+ Maxim Integrated Products, MAX17528GTJ+ Datasheet - Page 35

• Manufacturer Part Number: MAX17528GTJ+
• Description: IC PWM CTRLR STP-DWN 32TQFN-EP
• Manufacturer: Maxim Integrated Products
• Series: Quick-PWM™r

Specifications of MAX17528GTJ+

• Applications: Controller, Intel IMVP-6.5™ GMCH
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 0.01 ~ 1.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The internal pulldown transistor that drives DL low is
robust, with a 0.25Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs
when the inductor node (LX) quickly switches from
ground to V
long inductive driver traces must guarantee rising LX
edges do not pull up the low-side MOSFET’s gate, caus-
ing shoot-through currents. The capacitive coupling
between LX and DL created by the MOSFET’s gate-to-
drain capacitance (C
(C
not exceed the following minimum threshold:
Typically, adding a 4700pF between DL and power
ground (C
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
the turn-off time (R
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing five factors dictate the rest of the design:
•
ISS
Input voltage range: The maximum value
(V
AC adapter voltage. The minimum value (V
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
IN(MAX)
- C
RSS
IN
NL
), and additional board parasitics should
) must accommodate the worst-case high
. Applications with high input voltages and
in Figure 11), close to the low-side
V
GS TH
______________________________________________________________________________________
BST
(
RSS
in Figure 11). Slowing down the
)
<
), gate-to-source capacitance
V
Design Procedure
IN
⎛
⎝ ⎜
C
C
RSS
ISS
Intel IMVP-6.5/GMCH Controllers
Quick-PWM
⎞
⎠ ⎟
IN(MIN)
)
Figure 11. Gate-Drive Circuit
•
•
Maximum load current: There are two values to
consider. The peak load current (I
determines the instantaneous component stresses
and filtering requirements, and thus, drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
ous load current (I
stresses, and thus, drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Modern notebook CPUs gen-
erally exhibit I
Load line (voltage positioning): The load line (out-
put voltage vs. load slope) dynamically lowers the
output voltage in response to the load current, reduc-
ing the output capacitance requirement and the
processor’s power dissipation. The Intel specification
clearly defines the load-line requirement in the power-
supply specifications for each processor family.
(R BST )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
(C NL )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
THE SWITCHING NODE RISE TIME.
1-Phase Quick-PWM
MAX17528
PGND
LOAD
BST
V
DH
LX
DL
DD
C
= I
BYP
LOAD
(R
(C
BST
LOAD(MAX)
C
NL
BST
)*
)*
) determines the thermal
x 80%.
N
N
H
L
INPUT (V
LOAD(MAX)
L
IN
)
35
)