L6714 STMicroelectronics, L6714 Datasheet - Page 47

• Manufacturer Part Number: L6714
• Description: IC CTRLR 4PH W/DRIVERS 64-TQFP
• Manufacturer: STMicroelectronics

Specifications of L6714

• Applications: Controller, Intel VR10, VR11, AMD CPU
• Voltage - Input: 12V
• Number Of Outputs: 4
• Voltage - Output: 0.3 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Mounting Style: SMD/SMT
• Case: QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L6714
16
16.1
16.2
Preliminary over voltage
Output voltage monitor and protections
L6714 monitors through pin VSEN the regulated voltage in order to manage the OVP, UVP
and PGOOD (when applicable) conditions. The device shows different thresholds when
programming different operation mode (Intel or AMD,
response to a protection event is still the same as described below.
Protections are active also during soft-start
during D-VID transitions with an additional 32 clock cycle delay after the transition has
finished to avoid false triggering.
Under voltage
If the output voltage monitored by VSEN drops more than -750mV below the programmed
reference for more than one clock period, L6714 turns off all MOSFET and latches the
condition: to recover it is required to cycle Vcc or the OUTEN pin. This is independent of the
selected operative mode.
To provide a protection while VCC is below the UVLO
damage to the CPU in case of failed HS MOSFET. In fact, since the device is supplied from
the 12V bus, it is basically “blind” for any voltage below the turn-on threshold (UVLO
order to give full protection to the load, a preliminary-OVP protection is provided while VCC
is within UVLO
This protection turns-on the low side MOSFET as long as the FBR pin voltage is greater
than 1.800V with a 350mV hysteresis. When set, the protection drives the LS MOSFET with
a gate-to-source voltage depending on the voltage applied to VCCDRx and independently
by the turn-ON threshold across these pins (UVLO
the OUTEN pin status as detailed in
A simple way to provide protection to the output in all conditions when the device is OFF
(then avoiding the unprotected red region in
controller through the 5V
+12V and, in case of HS short, the LS MOSFET is driven with 5V assuring a reliable
protection of the load. Preliminary OVP is always active before UVLO
AMD Modes.
Figure 18. Output voltage protections and typical principle connections
UVLO
UVLO
VCC
OVP
V cc
Preliminary OVP
FBR Monitored
(OUTEN = 0)
VCC
and UVLO
Preliminary OVP Enabled
FBR Monitored
No Protection
SB
Provided
bus as shown in
Programmable OVP
OVP
VSEN Monitored
(OUTEN = 1)
.
Figure
(See “Soft start”
18.
Figure
Figure
Output voltage monitor and protections
VCCDR
18-Right: 5V
18-Left) consists in supplying the
+5V
VCC
+12V
See Table
SB
). This protection depends also on
threshold is fundamental to avoid
Section) while are masked
SB
10) but the behavior in
is always present before
VCC
for both Intel and
VCC
VCCDR1
VCCDR2
VCCDR3
VCC
47/70
). In