ISL6405ERZ Intersil, ISL6405ERZ Datasheet - Page 8

• Manufacturer Part Number: ISL6405ERZ
• Description: IC VOLT REG DUAL LNB 32-QFN
• Manufacturer: Intersil

Specifications of ISL6405ERZ

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This feature only affects the turn-on and programmed
voltage rise and fall times.
Current Limiting
The current limiting block has two thresholds that can be
selected by the ISEL bit of the SR and can work either
statically (simple current clamp) or dynamically. The lower
threshold is between 425mA and 530mA (ISEL = L), while
the higher threshold is between 775mA and 925mA
(ISEL = H). When the DCL (Dynamic Current Limiting) bit is
set to LOW, the over current protection circuit works
dynamically: as soon as an overload is detected, the output
is shutdown for a time t
the OLF bit of the System Register is set to HIGH. After this
time has elapsed, the output is resumed for a time t
20ms. During t
425mA or 775mA, depending on the ISEL bits. At the end of
t
cycle again through t
which no overload is detected, normal operation is resumed
and the OLF bit is reset to LOW. Typical t
920ms as determined by an internal timer. This dynamic
operation can greatly reduce the power dissipation in a short
circuit condition, still ensuring excellent power-on start-up in
most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1/2
bit goes HIGH when the current clamp limit is reached and
returns LOW when the overload condition is cleared. The
OLF1/2 bit will be LOW at the end of initial power-on soft-start.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds 150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to 135°C
(typical).
In over temperature conditions, the OTF Flag goes HIGH
and the I
monitor the I
enable the chip, if I
also make the OLF flags go HIGH, when high capacitive
loads are present or self-heating conditions occur at higher
loads.
External Output Voltage Selection
The output voltage can be selected by the I
Additionally, the QFN package offers two pins (SEL18V1,
SEL18V2) for independent 13V/18V output voltage
selection. When using these pins, the I
initialized to 13V status.
ON
, if the overload is still detected, the protection circuit will
2
C data will be cleared. The user may need to
2
C enable bits and OTF flag continuously and
ON
, the device output will be current limited to
2
C data is cleared. OTF conditions may
OFF
OFF
and t
, typically 900ms. Simultaneously
8
ON
. At the end of a full t
2
C bits should be
ON
2
C bus.
+ t
OFF
ON
time is
ON
=
in
ISL6405
I
(Refer to Philips I
Data transmission from main microprocessor to the ISL6405
and vice versa takes place through the two wire I
interface, consisting of the two lines SDA and SCL. Both SDA
and SCL are bidirectional lines, connected to a positive supply
voltage via a pull up resistor. (Pull up resistors to positive supply
voltage must be externally connected). When the bus is free,
both lines are HIGH. The output stages of ISL6405 will have an
open drain/open collector in order to perform the wired-AND
function. Data on the I
in the standard-mode or up to 400Kbps in the fast-mode. The
level of logic “0” and logic “1” is dependent of associated value
of V
generated for each data bit transferred.
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is
LOW. Refer to Figure 1.
START and STOP Conditions
As shown in Figure 2, START condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
2
SDA
SCL
SDA
SCL
C Bus Interface for ISL6405
DD
CONDITION
START
I
as per electrical specification table. One clock pulse is
2
S
C BITS
FIGURE 2. START AND STOP WAVEFORMS
13V
14V
13V
14V
DATA VALID
DATA LINE
STABLE
2
FIGURE 1. DATA VALIDITY
C Specification, Rev. 2.1)
2
C bus can be transferred up to 100Kbps
TABLE 1.
ALLOWED
SEL18V (1, 2)
CHANGE
OF DATA
High
High
Low
Low
O/P VOLTAGE
2
C bus
CONDITION
13V
14V
18V
19V
STOP
P