ISL6405ERZ Intersil, ISL6405ERZ Datasheet - Page 9

• Manufacturer Part Number: ISL6405ERZ
• Description: IC VOLT REG DUAL LNB 32-QFN
• Manufacturer: Intersil

Specifications of ISL6405ERZ

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

START
SDA
SCL
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6405 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
FIGURE 3. ACKNOWLEDGE ON THE I
R, W
R, W
SR1
SR2
MSB
1
2
ISEL2
R, W
R, W
9
DCL
8
2
C BUS
ACKNOWLEDGE
TABLE 3. SYSTEM REGISTER 1 (SR1)
TABLE 4. SYSTEM REGISTER 2 (SR2)
FROM SLAVE
ISEL1
ENT2
R, W
R, W
9
ISL6405
ENT1
LLC2
R, W
R, W
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6405 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
• A start condition (S)
• A chip address byte (MSB on left; the LSB bit determines
• A sequence of data (1 byte + Acknowledge)
• A stop condition (P)
System Register Format
All bits reset to 0 at Power-On
• R, W = Read and Write bit
• R = Read-only bit
S 0 0 0 1 0 0 0 R/W ACK
read (1) or write (0) transmission) (the assigned I
address for the ISL6405 is 0001 00XX)
VSEL2
LLC1
R, W
R, W
TABLE 2. INTERFACE PROTOCOL
VSEL1
R, W
R, W
EN2
R, W
EN1
OTF
R
Data (8 bits)
OLF1
OLF2
2
C slave
ACK P
R
R