L6712D STMicroelectronics, L6712D Datasheet - Page 19

IC CTRLR DC/DC 2PHASE 28-SOIC

L6712D

Manufacturer Part Number
L6712D
Description
IC CTRLR DC/DC 2PHASE 28-SOIC
Manufacturer
STMicroelectronics
Type
Step-Down (Buck)r
Datasheet

Specifications of L6712D

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
2
Voltage - Output
0.9 ~ 3.3 V
Current - Output
2A
Frequency - Switching
150kHz
Voltage - Input
12V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Power - Output
2W
Operating Temperature Range
- 40 C to + 125 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-5364-5
L6712D

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it. The voltage drop due to the output capacitor discharge is given by the following equation:
Where D
load transient and the lower is the output voltage static ripple.
3.11 INDUCTOR DESIGN
The inductance value is defined by a compromise between the transient response time, the efficiency, the
cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation
to maintain the ripple current ∆I
value can be calculated with this relationship:
Where F
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the con-
verter response time to a load transient. The response time is the time required by the inductor to change
its current from initial to final value. Since the inductor has not finished its charging time, the output current
is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during
the application of the load the inductor is charged by a voltage equal to the difference between the input
and the output voltage, during the removal it is discharged only by the output voltage. The following ex-
pressions give approximate response time for ∆I load transient in case of enough fast compensation net-
work response:
The worst condition depends on the input voltage available and the output voltage selected. Anyway the
worst case is the response time after removal of the load with the minimum output voltage programmed
and the maximum input voltage available.
3.12 MAIN CONTROL LOOP
The system control loop topology depends on the DROOP pin connection: if connected to FB (droop func-
tion active) an Average Current Mode topology must be considered while, if connected to GND (droop
function not active) a Voltage Mode topology must be considered instead.
Anyway, the system control loop encloses the Current Sharing control loop to allow proper sharing to the
inductor' currents. Each loop gives, with a proper gain, the correction to the PWMs in order to minimize
the error in its regulation: the Current Sharing control loop equalize the currents in the inductors while the
output voltage control loop fixes the output voltage equal to the reference programmed by VID (with or
without the droop effect and with or without considering the Remote Amplifier Gain). Figure 16 reports the
block diagram of the main control loop.
SW
MAX
is the switching frequency, V
is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during
t
application
∆V
L
between 20% and 30% of the maximum output current. The inductance
OUT
=
=
L
----------------------------- -
V
IN
IN
------------------------------------------------------------------------------- -
4 C
=
is the input voltage and V
L ∆I
V
----------------------------- -
V
IN
OUT
fs ∆I
OUT
V
∆I
OUT
(
L
V
2
In
OUT
V
-------------- -
d
V
t
OUT
max
removal
IN
L
V
OUT
=
OUT
-------------- -
V
L ∆I
OUT
)
is the output voltage.
L6712A L6712
19/29

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