SDCFIR-001G-388 SanDisk, SDCFIR-001G-388 Datasheet - Page 50

• Manufacturer Part Number: SDCFIR-001G-388
• Description: COMPACT FLASH IND 1GB
• Manufacturer: SanDisk

Specifications of SDCFIR-001G-388

• Memory Size: 1GB
• Memory Type: CompactFLASH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 585-1234; SDCFIR-001G-388

SanDisk Industrial Grade CompactFlash 5000
4.5.10
This register is used to control the CompactFlash Memory Card interrupt
request and to issue an ATA soft reset to the card. The bits are defined as
follows:
4.5.11
This register is provided for compatibility with the AT disk drive interface. This
register should not be mapped into the host's I/O space because of potential
conflicts on Bit 7. The bits are defined as follows:
© 2007 SanDisk® Corporation
D7
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Bit
Device Control Register
Card (Drive) Address Register (Address–3F7[377];
Offset Fh)
X
D7
D7
X
X
Name
X
X
X
X
1
SW Rst
-IEn
ERR
Name
-WTG
bus when this bit is provided by a Floppy Disk Controller operating at the same
addresses as the CompactFlash Memory Card. Following are some possible
solutions to this problem for the PCMCIA implementation:
1)
2)
3)
4)
This bit is unknown. Implementation Note: Conflicts may occur on the host data
D6
D6
X
Locate the CompactFlash Memory Card at a non-conflicting address, i.e.,
Secondary address (377) or in an independently decoded Address Space
when a Floppy Disk Controller is located at primary addresses.
Do not install a Floppy and a CompactFlash Memory Card in the system at
the same time
Implement a socket adapter that can be programmed to (conditionally) tri-
state D7 of I/0 address 3F7/377 when a CompactFlash Memory Card is
installed and conversely to tri-state D6-D0 of I/O address 3F7/377 when a
floppy controller is installed
Do not use the card's Drive Address Register. This can be accomplished by
either programming the host adapter to enable only I/O addresses 1F0-1F7,
Irrelevant.
Irrelevant.
Irrelevant.
Irrelevant.
Bit ignored by the card.
Set to 1 in order to force the card to perform an AT Disk controller
Soft Reset operation. This does not change the PCMCIA Card
Configuration registers as a hardware reset does. The card
remains in Reset until this bit is reset to “0”.
Interrupt Enable bit enables interrupts when the bit is 0. When the
bit is 1, interrupts from the card are disabled. This bit also controls
the Int bit in the Configuration and Status Register. This bit is set
to 0 at power on and reset.
Bit ignored by the card.
-HS3
D5
D5
X
-HS2
D4
D4
X
43
(Address–3F6[376]; Offset Eh)
-HS1
Description
D3
D3
1
Description
SW Rst
-HS0
D2
D2
-nDS1
-IEn
D1
D1
-nDS0
D0
D0
0
Product Manual
July 2007