MT4LSDT864HY-133G2 Micron Technology Inc, MT4LSDT864HY-133G2 Datasheet - Page 11

• Manufacturer Part Number: MT4LSDT864HY-133G2
• Description: MODULE SDRAM 64MB 144-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4LSDT864HY-133G2

• Memory Type: SDRAM
• Memory Size: 64MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Commands
able commands. This is followed by written descrip-
tion of each command.
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
09005aef80748a77
SD4C4_8_16X64HG.fm - Rev. C 6/04 EN
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
1. A0–A11 (32MB and 64MB) , or A0–A12 (128MB) provide device row address, and BA0, BA1 determine which device bank
2. A0–A7 (32MB) or A0–A8 (64MB and 128MB) provide device column address; A10 HIGH enables the auto precharge fea-
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register; for 32MB and 64MB, A12 should be driven low.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
The Truth Table provides a quick reference of avail-
is made active.
ture (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is
being read from or written to.
BA0, BA1 are “Don’t Care.”
Truth Table – SDRAM Commands and DQMB Operation
For a more detailed des-
CS# RAS# CAS# WE# DQMB
H
L
L
L
L
L
L
L
L
–
–
11
cription of commands and operations, refer to the
64Mb, 128Mb, or 256Mb SDRAM component data
sheet.
X
H
H
H
H
L
L
L
L
–
–
32MB, 64MB, 128MB (x64, SR)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
H
H
H
H
X
L
L
L
L
–
–
144-PIN SDRAM SODIMM
H
H
H
H
X
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
8
8
Bank/Col
Bank/Col
Op-code
ADDR
Bank/
©2004 Micron Technology, Inc. All rights reserved.
Code
Row
X
X
X
X
–
–
High-Z
Active
Active
Valid
DQ
X
X
X
X
X
X
X
NOTES
4
,
1
2
2
3
6
7
7
5