MT4VDDT3232UY-6K1 Micron Technology Inc, MT4VDDT3232UY-6K1 Datasheet - Page 15

• Manufacturer Part Number: MT4VDDT3232UY-6K1
• Description: MODULE DDR 128MB 167MHZ 172-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3232UY-6K1

• Memory Type: DDR SDRAM
• Memory Size: 128MB
• Speed: 333MT/s
• Package / Case: 172-UDIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 100UDIMM
• Device Core Size: 32b
• Organization: 32Mx32
• Total Density: 128MByte
• Chip Density: 256Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 700mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 100
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14: Capacitance (All Modules)
Note: 11; notes appear following parameter tables.
Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12–15, 29, 49; notes appear on pages 17–20; 0°C
pdf: 09005aef808da768, source: 09005aef808d2e9a
DD4C16_32x32UG.fm - Rev. D 9/04 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQ from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
PARAMETER
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CK, CK#, CKE
Operating Conditions
CL = 2.5
CL = 2
SYMBOL
t
t
CK (2.5)
t
t
DQSCK
t
t
t
t
15
t
CK (2)
DQSH
DQSQ
t
DIPW
DQSL
DQSS
t
t
t
t
MRD
t
t
t
t
DSH
t
t
QHS
t
t
t
IPW
RAS
T
t
DSS
t
t
t
DH
QH
AC
CH
HP
HZ
IH
IH
DS
CL
LZ
IS
IS
A
F
S
F
S
+70°C; V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
MIN
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
-0.7
-0.6
-0.7
QHS
HP -
7.5
0.2
0.2
0.8
0.8
2.2
12
42
6
t
DD
CH,
-6
SYMBOL
= V
t
70,000
CL
+0.70
MAX
+0.7
0.55
0.55
+0.6
0.45
1.25
0.60
64MB, 128MB (x32, SR)
C
C
13
13
DD
IO
I1
Q = +2.5V ±0.2V
100-PIN DDR UDIMM
t
-0.75
-0.75
-0.75
t
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
QHS
HP -
7.5
0.5
0.5
0.2
0.2
2.2
10
15
40
1
1
-75Z/-75
t
CH,
©2004 Micron Technology, Inc. All rights reserved.
120,000
t
MIN
CL
+0.75
+0.75
+0.75
MAX
0.55
0.55
1.25
0.75
4
8
0.5
13
13
MAX
12
5
UNITS NOTES
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
CK
CK
CK
CK
CK
UNITS
38, 47
38, 47
23, 27
23, 27
22, 23
16, 43
16, 43
22, 23
31, 50
pF
pF
26
26
27
30
12
12
12
12