MT8LSDT3264AY-133D2 Micron Technology Inc, MT8LSDT3264AY-133D2 Datasheet - Page 24

• Manufacturer Part Number: MT8LSDT3264AY-133D2
• Description: MODULE SDRAM 256MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8LSDT3264AY-133D2

• Memory Type: SDRAM
• Memory Size: 256MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.08A
• Number Of Elements: 8
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1228; MT8LSDT3264AY-133D2

Table 21:
Table 22:
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
Parameter/Condition
Parameter/Condition
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: I
INPUT LEAKAGE CURRENT: V
OUTPUT LEAKAGE CURRENT: V
STANDBY CURRENT: SCL = SDA = V
All other inputs = GND or 3.3V ±10%
POWER SUPPLY CURRENT:
SCL Clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition
can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1
OUT
IN
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= 3mA
OUT
= GND to V
and the falling or rising edge of SDA.
write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
DD
= GND to V
- 0.3V;
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
SS
SS
DD
; V
; V
DDSPD
DDSPD
DD
= +2.3V to +3.6V
= +2.3V to +3.6V
Symbol
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
24
t
HIGH
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
t
R
F
I
t
WRC) is the time from a valid stop condition of a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
I
Symbol
I
CC
CC
V
V
I
V
V
I
CCS
Write
I
LO
Read
DD
OL
LI
IH
MIN
IL
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
0
V
DD
MAX
MIN
300
400
0.9
0.3
50
10
-1
3
–
–
–
–
–
–
x 0.7
Serial Presence-Detect
©2003 Micron Technology, Inc. All rights reserved.
V
V
DD
DD
Units
MAX
KHz
3.6
0.4
ms
10
10
30
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
3
1
+ 0.5
x 0.3
Notes
Units
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4