MT9VDDT6472HG-335D2 Micron Technology Inc, MT9VDDT6472HG-335D2 Datasheet - Page 11
![MODULE DDR SDRAM 512MB 200SODIMM](/photos/7/83/78349/mfg_mt_sodimm_series_sml.jpg)
MT9VDDT6472HG-335D2
Manufacturer Part Number
MT9VDDT6472HG-335D2
Description
MODULE DDR SDRAM 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDT3272HG-335G2.pdf
(15 pages)
Specifications of MT9VDDT6472HG-335D2
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
167MHz
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
64Mx72
Total Density
512MByte
Chip Density
512Mb
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.575A
Number Of Elements
9
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1139
Table 11:
PDF: 09005aef80804052/Source: 09005aef806e057b
DD9C16_32_64x72H.fm - Rev. E 1/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
changing once per clock cycle; Address and control inputs
changing once every two clock cycles
Operating one bank active-read-precharge current:
BL = 4;
and control inputs changing once per clock cycle
Precharge power-down standby current: All device banks
idle; Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
inputs changing once per clock cycle; V
and DQS
Active power-down standby current: One device bank
active; Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank active;
DM, and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle;
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle;
DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
change only during active READ or WRITE commands
RC =
CK =
RC =
t
t
t
RC (MIN);
RC (MIN);
CK (MIN); CKE = HIGH; Address and other control
t
RC =
t
I
Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the
256Mb (32 Meg x 8) component data sheet
RC (MIN);
DD
t
t
CK =
CK =
Specifications and Conditions – 256MB
t
RC =
t
t
CK (MIN); DQ, DM, and DQS inputs
CK (MIN); Address and control inputs
t
CK =
t
t
CK =
RAS (MAX);
t
CK =
128MB, 256MB, 512MB (x72, ECC, SR) 200-Pin DDR SDRAM SODIMM
t
CK (MIN); I
t
t
t
CK =
CK =
CK (MIN); CKE = LOW
t
CK (MIN); CKE = LOW
t
t
CK (MIN); I
CK (MIN); DQ, DM, and
IN
t
CK =
= V
OUT
REF
t
t
(MIN)
t
CK (MIN); DQ,
REFC =
REFC = 7.8125µs
= 0mA; Address
for DQ, DM,
OUT
t
= 0mA
RFC
11
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
0
1
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1,215
1,530
1,800
1,755
2,340
4,230
-40B
540
360
630
36
54
36
1,125
1,530
1,575
1,575
2,295
3,690
-335
450
270
540
36
54
36
Electrical Specifications
©2004 Micron Technology, Inc. All rights reserved
1,125
1,440
1,350
1,350
2,115
3,150
-262
405
225
450
36
54
36
1,080
1,305
1,350
1,350
2,205
3,285
-265
405
270
450
36
54
36
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA