MT36VDDF25672Y-335F2 Micron Technology Inc, MT36VDDF25672Y-335F2 Datasheet - Page 12
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MT36VDDF25672Y-335F2
Manufacturer Part Number
MT36VDDF25672Y-335F2
Description
MODULE DDR 2GB 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT36VDDF25672G-335D2.pdf
(37 pages)
Specifications of MT36VDDF25672Y-335F2
Memory Type
DDR SDRAM
Memory Size
2GB
Speed
333MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 8:
NOTE:
Table 9:
pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
LENGTH
1. For a burst length of two, A1–Ai select the two-data-
2. For a burst length of four, A2–Ai select the four-data-
3. For a burst length of eight, A3–Ai select the eight-data-
4. Whenever a boundary of the block is reached within a
5. i = 9, 11 (1GB)
BURST
element block; A0 selects the first access within the
block.
element block; A0–A1 select the first access within the
block.
element block; A0–A2 select the first access within the
block.
given sequence above, the following access wraps
within the block.
i = 9, 11, 12 (2GB)
2
4
8
SPEED
-26A
-335
-262
-265
-202
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
75
75
75
75
75
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK FREQUENCY (MHZ)
CL = 2
ALLOWABLE OPERATING
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
f
f
f
f
f
SEQUENTIAL
133
133
133
100
100
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
ORDER OF ACCESSES
0-1
1-0
WITHIN A BURST
75
75
75
75
75
INTERLEAVED
CL = 2.5
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
f
f
f
f
f
0-1
1-0
167
133
133
133
125
12
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 8, CAS
Latency Diagram.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Figure 9,
CAS Latency (CL) Table, indicates the operating fre-
quencies at which each CAS latency setting can be
used.
ation or incompatibility with future versions may result.
Operating Mode
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
COMMAND
COMMAND
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown oper-
The normal operating mode is selected by issuing a
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 8: CAS Latency Diagram
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
1GB, 2GB (x72, ECC, DR)
184-PIN DDR RDIMM
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n