MT8VDDT6464AY-40BD3 Micron Technology Inc, MT8VDDT6464AY-40BD3 Datasheet - Page 7

• Manufacturer Part Number: MT8VDDT6464AY-40BD3
• Description: MODULE DDR 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464AY-40BD3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 4:
PDF: 09005aef80a43556, Source: 09005aef80a43534
DDA8C16_32_64x64AG_2.fm - Rev. E 4/06 EN
5, 14, 25, 36, 56, 67, 78, 86
97, 107, 119, 129, 149, 159,
115
27, 29, 32, 37, 41, 43, 48,
16, 17, 75, 76, 137, 138
122, 125, 130, 141
(256MB,
Pin Numbers
63, 65, 154
169, 177
52, 59
157
21
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information
512MB), 118,
WE#, CAS#, RAS#
CK1#, CK2, CK2#
(256MB, 512MB)
CK0, CK0#, CK1,
DQS0–DQS7
DM0
BA0, BA1
Symbol
(128MB)
A0–A11
A0–A12
CKE0
128MB, 256MB, 512MB (x64, SR): PC3200 184-Pin DDR UDIMM
S0#
–
DM7
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Type
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers, and output drivers. Taking
CKE LOW provides precharge power-down and SELF REFRESH
operations (all device banks idle), or active power-down (row
ACTIVE in any device bank). CKE is synchronous for power-
down entry and exit, and for SELF REFRESH entry. CKE is
asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during power-down. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
until CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
Chip selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data write mask: DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
7
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Pin Assignments and Descriptions
Description
©2005 Micron Technology, Inc. All rights reserved.
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