MT8VDDT6464HDG-40BF2 Micron Technology Inc, MT8VDDT6464HDG-40BF2 Datasheet - Page 8

• Manufacturer Part Number: MT8VDDT6464HDG-40BF2
• Description: MODULE DDR 512MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464HDG-40BF2

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

leaved), A4–A6 specify the CAS latency, and A7–A12
specify the operating mode.
Burst Length
burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5 for Figure 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. The programmed burst length
applies to both READ and WRITE bursts.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in Figure 6, Burst
Definition Table, on page 9.
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, 2.5, or 3 clocks, as shown in Figure 5,
CAS Latency Diagram.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9 indicates the oper-
ating frequencies at which each CAS latency setting
can be used.
pdf: 09005aef80b575ca, source: 09005aef806e1d28
DDA8C32_64x64HDG.fm - Rev. D 9/04 EN
Read and write accesses to DDR SDRAM devices are
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
8
operation or incompatibility with future versions may
result.
Operating Mode
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
256MB, 512MB (x64, DR) PC3200
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Reserved states should not be used as unknown
The normal operating mode is selected by issuing a
Figure 4: Mode Register Definition
0*
14
BA1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0*
13
BA0
12
A12 A11
Operating Mode
11
M13
0
0
-
10
A10
M12 M11
0
0
-
9
200-PIN DDR SODIMM
A9
0
0
-
8
A8
M10
0
0
-
Diagram
7
A7 A6 A5 A4 A3
M9
CAS Latency BT
M6
0
0
-
0
0
0
0
1
1
1
1
6
M8 M7
0
1
M5
-
0
0
1
1
0
0
1
1
5
0
0
-
M4
0
1
0
1
0
1
0
1
4
M6-M0
M3
0
1
Valid
Valid
3
-
Burst Length
M2
2
0
0
0
0
1
1
1
1
A2 A1 A0
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M1
0
0
1
1
0
0
1
1
1
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
2.5
2
M0
©2004 Micron Technology, Inc.
0
1
0
1
0
1
0
1
0
Burst Type
Interleaved
Sequential
Burst Length
Mode Register (Mx)
Reserved
Reserved
Reserved
Reserved
Reserved
M3 = 0
Address Bus
2
4
8