MT9VDDF6472Y-40BF3 Micron Technology Inc, MT9VDDF6472Y-40BF3 Datasheet - Page 10
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MT9VDDF6472Y-40BF3
Manufacturer Part Number
MT9VDDF6472Y-40BF3
Description
MODULE DDR 512MB 184-DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT9VDDF6472Y-40BF1.pdf
(30 pages)
Specifications of MT9VDDF6472Y-40BF3
Memory Type
DDR SDRAM
Memory Size
512MB
Speed
400MT/s
Package / Case
184-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 6:
NOTE:
Table 7:
pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23
DDAF9C32_64x72G.fm - Rev. C 9/04 EN
LENGTH
1. For a burst length of two, A1–Ai select the two-data-
2. For a burst length of four, A2–Ai select the four-data-
3. For a burst length of eight, A3–Ai select the eight-data-
4. Whenever a boundary of the block is reached within a
5. i = 9 for 256MB
BURST
SPEED
element block; A0 selects the first access within the
block.
element block; A0–A1 select the first access within the
block.
element block; A0–A2 select the first access within the
block.
given sequence above, the following access wraps
within the block.
i = 9, 11 for 512MB
2
4
8
-40B
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
75
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
CL = 2
f
A0
CLOCK FREQUENCY (MHZ)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
ALLOWABLE OPERATING
133
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
75
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
CL = 2.5
0-1
1-0
f
A BURST
133
INTERLEAVED
133
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
CL = 3
0-1
1-0
f
200
256MB, 512MB (x72, ECC, SR) PC3200
10
Read Latency
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 6,
CAS Latency Diagram.
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, indicates the operating fre-
quencies at which each CAS latency setting can be
used.
operation or incompatibility with future versions may
result.
Operating Mode
MODE REGISTER SET command with bits A7–A12
each set to zero, and bits A0–A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
COMMAND
COMMAND
COMMAND
The READ latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by issuing a
DQS
DQS
DQS
CK#
CK#
CK#
DQ
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 6: CAS Latency Diagram
CK
CK
CK
184-PIN DDR SDRAM RDIMM
READ
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
NOP
T1
T1
T1
CL = 3
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
NOP
T2
T2
T2n
T2n
T2n
DON’T CARE
T3
NOP
NOP
NOP
T3
T3
T3n
T3n
T3n