MT9VDVF6472Y-335D4 Micron Technology Inc, MT9VDVF6472Y-335D4 Datasheet - Page 31

• Manufacturer Part Number: MT9VDVF6472Y-335D4
• Description: MODULE DDR 512MB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT9VDVF6472Y-335D4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Package Type: VLP DIMM
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 1.575A
• Number Of Elements: 9
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17:
PDF: 09005aef81cf6969/Source: 09005aef81cf67b0
DVF9C32_64x72_2.fm - Rev. A 8/05 EN
Parameter
Operating Clock Frequency
Input Duty Cycle
Stabilization Time
Cycle to Cycle Jitter
Static Phase Offset
Output Clock Skew
Period Jitter
Half-Period Jitter
Input Clock Slew Rate
Output Clock Slew Rate
PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Notes: 1. Timing and switching specifications for the PLL listed above are critical for proper opera-
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be
7. The Output Slew Rate is determined from the IBIS model:
tion of DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters
for the specific device used on the module. Detailed information for this PLL is available in
JEDEC Standard JESD82.
in which it is not required to meet the other timing parameters. (Used for low-speed sys-
tem debug.)
its feedback signal to its reference signal after power up.
met independently of each other.
Symbol
t
t
t
JIT
t
STAB
JIT
t
t
t
JIT
CDCV857
f
t
SK
t
LS
CK
DC
LS
∅
HPER
PER
CC
O
GND
O
V
I
DD
Min
-100
-75
-50
-75
1.0
1.0
60
40
-
-
256MB, 512MB: (x72, SR) 184-Pin DDR VLP RDIMM
V
V
CK
CK
R=60
R=60
Ω Ω Ω Ω
Ω Ω Ω Ω
V
31
0°C ≤ T
DD
V
DD
Nominal
/2
= +2.5V ±0.2V
0
-
-
-
-
-
-
-
-
-
A
≤ +70°C
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PLL and Register Specifications
Max
170
100
100
100
75
50
75
60
4
2
©2004 Micron Technology, Inc. All rights reserved.
Units
MHz
V/ns
V/ns
ms
%
ps
ps
ps
ps
ps
Notes
2, 3
4
5
6
6
7