MT16VDDT6464AY-40BGB Micron Technology Inc, MT16VDDT6464AY-40BGB Datasheet
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MT16VDDT6464AY-40BGB
Specifications of MT16VDDT6464AY-40BGB
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MT16VDDT6464AY-40BGB Summary of contents
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... DDR SDRAM UDIMM MT16VDDT3264A – 256MB MT16VDDT6464A – 512MB MT16VDDT12864A – 1GB MT16VDDT25664A – 2GB (ADVANCE) For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 184-Pin DIMM (MO-206) Standard 1.25in. (31.75mm) Low-Profile 1.15in. (29.21mm) OPTIONS • Package 184-pin DIMM (standard) 184-pin DIMM (lead-free) • ...
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... PART NUMBER MODULE DENSITY MT16VDDT3264AG-335__ MT16VDDT3264AY-335__ MT16VDDT3264AG-262__ MT16VDDT3264AY-262__ MT16VDDT3264AG-26A__ MT16VDDT3264AY-26A__ MT16VDDT3264AG-265__ MT16VDDT3264AY-265__ MT16VDDT6464AG-335__ MT16VDDT6464AY-335__ MT16VDDT6464AG-262__ MT16VDDT6464AY-262__ MT16VDDT6464AG-26A__ MT16VDDT6464AY-26A__ MT16VDDT6464AG-265__ MT16VDDT6464AY-265__ MT16VDDT12864AG-335__ MT16VDDT12864AY-335__ MT16VDDT12864AG-262__ MT16VDDT12864AY-262__ MT16VDDT12864AG-26A__ MT16VDDT12864AY-26A__ MT16VDDT12864AG-265__ MT16VDDT12864AY-265__ MT16VDDT25664AG-335__ MT16VDDT25664AY-335__ MT16VDDT25664AG-262__ MT16VDDT25664AY-262__ MT16VDDT25664AG-26A__ MT16VDDT25664AY-26A__ MT16VDDT25664AG-265__ MT16VDDT25664AY-265__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes ...
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Table 3: Pin Assignment (184-Pin DIMM Front PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 63, 65, 154 WE#, CAS#, RAS# 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, ...
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... V Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 184-PIN DDR SDRAM UDIMM DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. © ...
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... DD V REF V SS NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. pdf: 09005aef80739fa5, source: 09005aef807397e5 DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 256MB, 512MB, 1GB, 2GB (x64, DR) DQS4 ...
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... CAS# CKE0 CKE1 WE# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. pdf: 09005aef80739fa5, source: 09005aef807397e5 DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 256MB, 512MB, 1GB, 2GB (x64, DR) ...
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... DDR SDRAM modules use inter- nally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. Double data rate architecture is essentially a 2n-prefetch architec- ture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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... BA1 BA0 A10 A11 Operating Mode CAS Latency BT * M13 and M12 (BA0 and BA1) must be “0, 0” to select the base mode register (vs. the extended mode register). 512MB and 1GB Modules BA1 BA0 A12 A11 A10 Operating Mode CAS Latency BT * M14 and M13 (BA0 and BA1) must be “0, 0” to select the base mode register (vs ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM Figure 7: Extended Mode Register Definition Diagram 256MB Module BA1 BA0 A8 A11 A10 Operating Mode 512MB and 1GB Modules BA1 BA0 A10 A8 A12 A11 Operating Mode The 2GB Module BA1 BA0 ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN (MIN); DQ, ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM Components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 14: I Specifications and Conditions – 1GB DD DDR SDRAM Components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 15: I Specifications and Conditions – 2GB DD DDR SDRAM Components only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 20–23; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 16: Capacitance Note: 11; notes appear on pages 20–23 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#, CKE Input Capacitance: CK0, CK0# Input Capacitance: CK1, CK1#; CK2, CK2# Table 17: DDR SDRAM Component ...
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Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 13-15, 29, 48, 49; notes appear on pages 20–23; 0°C AC CHARACTERISTICS PARAMETER Address and control input setup time (slow slew rate) Address and Control ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM control- ler greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2), ...
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READs and WRITEs with auto precharge are not t allowed to be issued until RAS (MIN) can be satis- fied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less ...
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The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 13, Data Validity, and Figure ...
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Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device ...
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Table 22: Serial Presence-Detect Matrix (256MB, 512MB, and 1GB) (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION 28 Minimum Row Active to Row Active, t RRD 29 Minimum Ras# to CAS# Delay, ...
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... The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80739fa5, source: 09005aef807397e5 DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM ENTRY (VERSION) ...
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Table 23: Serial Presence-Detect Matrix (2GB) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 31 BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory ...
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... The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80739fa5, source: 09005aef807397e5 DD16C32_64_128_256x64AG.fm - Rev. C 9/04 EN 256MB, 512MB, 1GB, 2GB (x64, DR) 184-PIN DDR SDRAM UDIMM ENTRY (VERSION) ...
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Figure 17: 184-PIN DDR DIMM Dimensions – Standard PCB 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.091 (2.30) 0.050 (1.27) TYP. TYP. U19 U10 U11 PIN 184 1.95 (49.53) NOTE: All dimensions ...
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Figure 18: 184-PIN DDR DIMM Dimensions – Low-Profile PCB .00) R (4X .50) D (2X) 0) TYP. PIN 1 0.091 (2.30) 0.050 (1.27) TYP. TYP. U19 U18 PIN 184 NOTE: All dimensions arein inches (millimeters); Data Sheet Designation ...