MT18LSDT3272DG-133G1 Micron Technology Inc, MT18LSDT3272DG-133G1 Datasheet - Page 10
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MT18LSDT3272DG-133G1
Manufacturer Part Number
MT18LSDT3272DG-133G1
Description
MODULE SDRAM 256MB 168DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18LSDT6472G-133D2.pdf
(13 pages)
Specifications of MT18LSDT3272DG-133G1
Memory Type
SDRAM
Memory Size
256MB
Speed
133MHz
Package / Case
168-DIMM
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Register and PLL Specifications
Table 13:
Table 14:
PDF: 09005aef809b161a/Source: 09005aef809b15eb
SD18C32_64_128x72.fm - Rev. E 1/08 EN
Parameter
Parameter
Maximum clock pulse frequency
Propagation delay, single rank
(CK to output)
Propagation delay, dual rank
(CK to output)
Pulse duration
Setup time
Hold time
Operating clock frequency
Input duty cycle
Cycle-to-cycle jitter
Static phase offset
SSC induced skew
Output-to-output skew
Register Timing Requirements and Switching Characteristics
162835A device or equivalent JESD82-2
PLL Clock Driver Timing Requirements and Switching Characteristics
CDC2510 device or equivalent JESD82-5
Notes:
1. SSC = spread spectrum clock. The use of SSC synthesizers on the system motherboard will
2. Skew is defined as the total clock skew between any two outputs and, therefore, is speci-
reduce EMI.
fied as a maximum only.
Symbol
f
t
t
MAX
256MB, 512MB, 1GB (x72, ECC, SR): 168-Pin SDRAM RDIMM
PD1
PD2
t
t
t
SU
W
H
Symbol
t
t
t
f
t
JIT
SSC
SK
DC
t
CK
∅
CC
O
50pF to GND and 50Ω to V
30pF to GND and 50Ω to V
Data before CK HIGH
Data after CK HIGH
CK, HIGH or LOW
Condition
10
–150
Min
–75
50
44
–
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TT
TT
Max
Register and PLL Specifications
140
150
150
150
55
75
Min
150
1.4
0.7
3.3
1.0
0.6
Units
©2003 Micron Technology, Inc. All rights reserved
MHz
%
ps
ps
ps
ps
Max
240
3.5
2.5
–
–
–
Notes
Units
1, 2
MHz
ns
ns
ns
ns
ns