MT18VDDF12872Y-335D3 Micron Technology Inc, MT18VDDF12872Y-335D3 Datasheet - Page 10

• Manufacturer Part Number: MT18VDDF12872Y-335D3
• Description: MODULE SDRAM DDR 1GB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDF12872Y-335D3

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 3.15A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

I
Table 9:
PDF: 09005aef8074e85b/Source: 09005aef8072fe49
DDF18C64_128x72.fm - Rev. F 9/08 EN
Parameter/Condition
Operating one bank active-precharge current:
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
cycle
Precharge power-down standby current: All device banks idle; Power-down
mode;
Idle standby current: CS# = HIGH; All device banks idle;
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
Active power-down standby current: One device bank active; Power-down
mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active
t
clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device bank
active; Address and control inputs changing once per clock cycle;
I
Operating burst write current: BL = 2; Continuous burst writes; One device
bank active; Address and control inputs changing once per clock cycle;
t
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank interleaving reads
(BL = 4) with auto precharge;
control inputs change only during active READ or WRITE commands
DD
OUT
CK =
RC =
CK =
IN
= V
Specifications
= 0mA
t
t
t
CK (MIN); I
RAS (MAX);
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
REF
t
t
CK =
CK =
for DQ, DM, and DQS
t
t
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
I
Values are shown for the MT46V64M4 DDR SDRAM only and are computed from values specified in the
256Mb (64 Meg x 4) component data sheet
DD
OUT
Specifications and Conditions – 512MB (Die Revision ‘K’)
t
CK =
= 0mA; Address and control inputs changing once per clock
t
CK (MIN); DQ, DM, and DQS inputs changing twice per
t
RC =
t
RC (MIN);
512MB, 1GB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
t
CK =
t
RC =
t
CK (MIN); Address and
t
RC (MIN);
t
CK =
t
t
10
REFC =
REFC = 7.8125µs
t
t
CK (MIN);
RC =
t
CK =
t
RFC (MIN)
t
CK =
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RC (MIN);
t
CK (MIN);
t
CK
;
Symbol
I
I
I
I
I
I
I
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
DD
4W
3N
5A
2P
3P
4R
2F
Electrical Specifications
0
1
5
6
7
©2003 Micron Technology, Inc. All rights reserved.
1,800
2,160
1,080
3,240
3,240
2,880
5,220
-40B
900
630
108
72
72
1,620
2,070
2,880
2,880
2,880
4,860
-335
900
540
990
108
72
72
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA